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Re: prefetch revisited
On Tue, Oct 30, 2001 at 08:38:50PM +0100, Jan Hubicka wrote:
> I've digged out one copy of my prefetch.c file. It should be basically working,
> but no guarantees.
I'd like to concentrate on the prefetch infrastructure for now and not
look at specific uses of it yet; I already have a version of your loop
optimizer changes to generate prefetch instructions, and at this point
I don't care if it's optimal or not. I would, however, greatly
appreciate your feedback about what capabilities of hardware prefetch
support you think would be useful within GCC. Those can be represented
in the RTL pattern for prefetch, and specific optimizations can choose
to use them or just pass default values.
In your patch you pass an address, and offset, and an int to
gen_prefetch; how is the offset used, and what is the int? IA-64 has a
base-update form of prefetch, which adds an offset value to the base
register. Is your offset for something like that? What do you do with
the offset on a machine that doesn't support a base-offset form of
I'm cleaning up my current changes so I can post a preliminary version
of the prefetch infrastructure patch for review, with support for ia64
and i386 (sse and 3dnow!). I'll put the update of your loop
optimization prefetch support in a separate patch to show how it's used.
Here's a preliminary description of the prefetch RTL information, based
on support in IA-64 and i386 variants; there might be fewer if some of
these aren't practical to use, or more if other machines have nifty
capabilities that GCC can exploit.
(prefetch addr off rw temploc cachelev)
Represents prefetch of memory at address addr plus offset off.
(Is the offset added before or after the prefetch?)
The other operands specify which capabilities of the machine's
prefetch support to use.
rw is a value for one of the following:
read or generic prefetch
write prefetch if available else nop
write prefetch if available else generic prefetch
temploc is a flag that is 1 if the prefetch should specify
cachelev is a value between 0 and 15, where 0 specifies the
nearest cache level available and 15 specifies the farthest cache
level; a machine description maps these to the cache levels
supported by its prefetch instructions.
This insn is used to improve memory access time when the address of
memory that is likely to be accessed is known far enough ahead of
time to make prefetching that memory worthwhile.
In the meantime, Jan, in between all of your other projects you can
continue to determine how to use prefetch in optimizations and provide
me with feedback, and eventually our work can converge.