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Re: Inefficient bitfield code generation


> - Consider such instructions while optimising in RTL

It's really another case where combine's focus on no more than three insns
and obvious producer-consumer chains is an obstacle for using it as a truely
general high-level peephole optimizer.

Maybe we should have another pre-register-allocation peephole optimizer,
more like peephole2 in the way it is driven, but like combine, allowing
other insns in-between as long as their register usage wouldn't make the
transformation invalid.

-- 
Joern Rennecke                  |            gcc expert for hire
amylaar@onetel.net.uk           |  send enquiries to: jwr_jobs@onetel.net.uk


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