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Re: Inefficient bitfield code generation


On 26 Oct, Zoltan Hidvegi wrote:

> the assembly is
> 
>         slwi 4,4,8
>         rlwimi 5,4,0,0,23
>         stw 5,0(3)

Actually the rs6000 port of gcc is really bad when it
comes to using the blazingly powerful rotate and mask
instructions of the powerpc. 

I see several different approaches to cure this performance
penalty:
- Consider such instructions while optimising in RTL
- Have better RTL->insn generators and splitters
- Have good peephole definitions

I haven't had the time to play around with either idea
but I'd definitely like being able to generate better code.

--
Servus,
       Daniel


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