This is the mail archive of the
mailing list for the GCC project.
Re: Inefficient bitfield code generation
- To: hzoli at austin dot ibm dot com
- Subject: Re: Inefficient bitfield code generation
- From: degger at fhm dot edu
- Date: Sat, 27 Oct 2001 14:24:46 +0200 (CEST)
- Cc: gcc at gcc dot gnu dot org
- Reply-To: degger at fhm dot edu
On 26 Oct, Zoltan Hidvegi wrote:
> the assembly is
> slwi 4,4,8
> rlwimi 5,4,0,0,23
> stw 5,0(3)
Actually the rs6000 port of gcc is really bad when it
comes to using the blazingly powerful rotate and mask
instructions of the powerpc.
I see several different approaches to cure this performance
- Consider such instructions while optimising in RTL
- Have better RTL->insn generators and splitters
- Have good peephole definitions
I haven't had the time to play around with either idea
but I'd definitely like being able to generate better code.