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Re: Unaligned double

> (insn 28 26 30 (set (subreg:SI (reg:DF 96) 1)
>          (reg:SI 102)) 68 {*} (nil)
>      (expr_list:REG_DEAD (reg:SI 102)
>          (nil)))
> which becomes:
> (insn 68 28 65 (set (reg:SI 43 %fr9R [42])
>          (reg:SI 21 %r21)) 68 {*} (nil)
>      (nil))

The way the insn number changes hints that this is probably done by combine.
You can verify this by displaying the insns in question before and after
the call to combine_instructions.  If this is the case, you can get a
closer look at what happens by setting a breakpoint at try_combine with
a condition i3->fld[0].rtint == 68.  If you are lucky, it is a straight
3-insn combination and you can use the condition
i3->fld[0].rtint == 68 && i1 && i1->fld[0].rtint == 28

Note that the subreg handling has been completely overhauled with the
CLASS_CANNOT_CHANGE_MODE_P in some instances where we don't need them
any longer.

pa32-regs.h is rather odd in that it defines CLASS_CANNOT_CHANGE_MODE
as NO_REGS and then goes on to define CLASS_CANNOT_CHANGE_MODE_P to
reject size-changing mode changes.  The latter is made ineffective by the

> (insn 68 28 30 (set (reg:SI 43 %fr9R [42])
>          (reg:SI 21 %r21)) 68 {*} (nil)
>      (nil))
> Internal compiler error in extract_constrain_insn_cached, at recog.c
>     :2133
> Please submit a full bug report,
> Note that I am using PA 1.0 as the architecture and %fr9R should not be
> used. In fact:

If a 32 bit floating point move is OK but the calculated register number
is wrong, you should look into defining SUBREG_REGNO_OFFSET.  Note that
the last time I looked, the framework for SUBREG_REGNO_OFFSET did not
work in some trivial manner, and needed fixing.

If a 32 bit floating point move is generally wrong, try defining

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