This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]

Re: The new scheduler and x86 CPUs

Toon Moene wrote:
> Vladimir Makarov wrote:
> >   I see
> > (
> > that Itanium has the same SPECint as UltrasparcIII practically on the
> > same frequency.  SPECfp is 2 times better,
> Yes, we all know Intel likes to compare the Itanium to the UltraSparc.
> Unfortunately, the only comparison relevant to *me* (before the 25th of
> June) was w.r.t. the Alpha.
> As a meteorologist, I'm mostly interested in the (SPECfp) performance on
> apsi:
> (, SPECfp2000 2nd half '01):
> Dell 1.7 Ghz Pentium IV:
>         apsi    base: 458       peak: 463
> HP server rx4610, 800 Mhz Itanium:
>         apsi    base: 342       peak: 342
> Compaq DS20, 833 Mhz Alpha EV67:
>         apsi    base: 543       peak: 544
> Yes, I know Alpha is dead - but that's no reason to argue revisionist
> history with respect to Out-Of-Order implementations.

Actually, Alpha was the last high end processor which gave up classical
superscalar RISC architecture in favor OOO approach.  That was my
favorite architecture.  I've took part in implementation of an
experimental C/C++ compiler for Alpha and knew Bob Morgan which took
part in designing Alpha processor as a compiler expert.  Actually the
dfa based scheduler was inspired by discussions of insn scheduling with
Norman Rubin which worked in DEC that time (his article is the best
article about DFA based scheduler).  They are very talented people.

  Dec bought Multiflow computer.  Multiflow VLIW architecture and
compiler failed for SPECInt kind of programs.  On my opinion because
that time the compiler guys was not enough smart for this architecture
(they used trace scheduling which is conceptually weaker than global
insns scheduling with making insn coping, partial register renaming and
forward substitution), the architecture had predictaion but had not EPIC
features data speculation, control speculations, big register file and
so on. So Dec has decided not to continue to design VLIW processors. 
That is pity. I am not fan of IA64 (I wrote that IA64 VLIW packing is
weird) but I do not see alternative to EPIC approach.  As I said, OOO is
solution for pure.  You need huge investments to make a good compiler
for EPIC.  So unfortunately money rules.  In the best time Dec had 7
compiler groups and finished with one compiler group.

As for the data, I see the following

Alpha 833Mhz: base : 643

Itanium 800 Mhz: base: 701

If 342 for Itanium were for gcc, I would not be surprised.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]