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Re: GCC 3.0 Status Report
- To: Bernd Schmidt <bernds at redhat dot com>
- Subject: Re: GCC 3.0 Status Report
- From: Geert Bosch <bosch at gnat dot com>
- Date: Tue, 12 Jun 2001 11:01:30 -0400 (EDT)
- Cc: Mark Mitchell <mark at codesourcery dot com>, gcc at gcc dot gnu dot org
On Tue, 12 Jun 2001, Bernd Schmidt wrote:
I've looked into this. There's something extremely weird going on in
the mips backend; the reload_outdi pattern generates uninitialized uses
(at least according to the rtl) of regs 64 and 65 (lo/hi). We end up
with a sequence of
(insn/i 213 437 452 (parallel[
(set (reg:DI 66 accum)
(mult:DI (zero_extend:DI (reg:SI 4 a0 [151]))
(zero_extend:DI (reg:SI 2 v0 [152]))))
(clobber (reg:DI 65 lo))
(clobber (reg:DI 64 hi))
] ) 41 {mulsidi3_64bit} (insn_list 211 (insn_list 212 (nil)))
(nil))
(insn 452 213 454 (set (reg:DI 6 a2)
(reg:DI 65 lo)) 154 {movdi_internal2} (nil)
(nil))
The mult instruction sets registers 64 and 65 to hold the lo and the
hi parts of the product (IIRC). Not knowing much about GCC internals,
I wouldn't know why that is marked as a clobber instead of a set,
Below is the relevant page from the MIPS documentation, see
<http://www.mips.com/Documentation/R4400_Uman_book_Ed2.pdf>
Appendix A
_______________________________________________________________________
MULT Multiply MULT
31 26 25 21 20 16 15 6 5 0
-------------------------------------------------------------
SPECIAL | rs | rt | 0 | MULT
0 0 0 0 0 0| | |0 0 0 0 0 0 0 0 0 0|0 1 1 0 0 0
-------------------------------------------------------------
6 5 5 10 6
Format:
MULT rs, rt
Description:
The contents of general registers rs and rt are multiplied,
treating both operands as 32-bit 2s complement values.
No integer overflow exception occurs under any circumstances.
In 64-bit mode, the operands must be valid 32-bit, sign-
extended values.
When the operation completes, the low-order word of the double
result is loaded into special register LO, and the high-order
word of the double result is loaded into special register HI.
If either of the two preceding instructions is MFHI or
MFLO, the results of these instructions are undefined.
Correct operation requires separating reads of HI or LO
from writes by a minimum of two other instructions.
_______________________________________________________________________
A-118 MIPS R4000 Microprocessor User's Manual