eliminable register problem

[Herman ten Brugge <Haj dot Ten dot Brugge at net dot HCC dot nl>]

Hello,

I have some problems with reload and parallel instruction on the
c4x target. The problems seems to be caused by incorrect handling
of eliminable registers.
After the lreg pass I have an insn that looks like:

(insn 20 19 21 (parallel[
            (set (reg:QI 41)
                (mem:QI (post_inc:QI (reg/f:QI 40)) 0))
            (set (mem:QI (plus:QI (reg/f:QI 59)
                        (const_int 1 [01h])) 0)
                (reg:QI 41))
        ] ) 10 {movqi_parallel} (insn_list 121 (insn_list 17 (insn_list 18 (nil))))
    (expr_list:REG_INC (reg/f:QI 40)
        (nil)))

Reload also finds an eliminable register that can replace the 
'(plus:QI (reg/f:QI 59) (const_int 1 [01h]))' part of this insn.
The replace is '(plus:QI (reg/f:QI 11 ar3) (const_int 2 [02h]))'.
The insn now looks like:

(insn 20 19 21 (parallel[ 
            (set (reg:QI 0 r0 [41])
                (mem:QI (post_inc:QI (reg/f:QI 9 ar1 [40])) 0))
            (set (mem:QI (plus:QI (reg/f:QI 11 ar3)
                        (const_int 2 [02h])) 0)
                (reg:QI 0 r0 [41]))
        ] ) 10 {movqi_parallel} (insn_list 121 (insn_list 17 (insn_list 18 (nil)
)))
    (expr_list:REG_INC (reg/f:QI 9 ar1 [40])
        (nil)))

The problem is that this insn is not valid anymore because the offset for
a register for parallel insns on the c4x can only be 1. 
After reload makes this faulty change it complains that the insn is not
valid anymore and can not recover from this.

This problem happens on the 3.0 and 3.1 release. The code that fails on 3.0 is
rather large and is also confidential. The 3.1 code that fails is:

.../gcc/testsuite/gcc.c-torture/execute/961213-1.c

When this code is compiled with '-O3 -m30' and the compiler is configured
with '--target=c4x' the above problem happens.

If I disable generating eliminable registers the problem goes away.

Do we do something wrong on the c4x target or is there a problem in reload?

Thanks.

	Herman.