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Re: P4 support question (-> FAQ?)


On Tuesday 29 May 2001 15:28, Tim Prince wrote:
> ----- Original Message -----
> From: "Jean Francois Martinez" <jfm2@club-internet.fr>
> To: "Will Menninger" <william.l.menninger@boeing.com>; <gcc@gcc.gnu.org>
> Sent: Thursday, May 24, 2001 10:22 AM
> Subject: Re: P4 support question (-> FAQ?)
>
> > On Thursday 24 May 2001 17:51, Will Menninger wrote:
> > > Hello,
> > >
> > > Is there a way to add a question to the gcc FAQ database on the web?
> > > Either way, I'd like to see this question added to the platform
>
> specific
>
> > > section (and hopefully answered):  What is the timeline (if any) for
> > > supporting Pentium 4 specific instructions (e.g. SSE-2) in gcc?  Is
>
> this
>
> > > being worked on or expected to occur in a specific release of gcc?
> > >
> > > Please refer me to the appropriate link if this question is answered
> > > somewhere in the gcc web pages.
> >
> > My experince with gcc 2.x is that use of specific instructions brings
>
> only
>
> > minimal sped increases in 99 % of cases, the real speed boost is given by
> > using sequences who are optimized for processor.  In other words -march=
> > (use of specific instructions) brins very little improvement over -mcpu=
> > (optimized for specific cpu but using only 386 instructions).
> >
> > This could change the day gcc genartes MMX instructions but for now the
> > question should be when will gcc be able to optimize for PIV?
> >
> > JFM
>
> I don't expect any changes in scheduling to make major differences in
> performance on P4; gcc already does quite well when P-II optimizations are
> selected.  I'm in the middle of a comparison of efficiency of code
> sequences generated by various compilers; while SSE code is required in
> many situations to make the best of P4, there are situations where gcc
> generates P-II compatible code which is faster than that available from
> commercial compilers.


My experience with the P6 family is that using P6-oriented scheduling made 
quite a difference (around 15% to 20%) over code compiled for Pentium.  In 
fact P5 scheduling was the worst thing you could do when program had to run 
on P6 (even programs compiled for 386 are faster).  Litterature about the 
Pentium IV tells the PIVb has different schedulings requirements then those 
of the P6 family and that PIV is more sensitive than P6 family to programs 
not being properlly scheduled so differnce should be bigger than the  15% 
performnce loss for Pentium code running on P6 family.

			JFM
  . 


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