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Re: stepanov on sparc; sparc backend scheduling issues



> 	Sigh.  On PowerPC, the first loops look like:

[ a loop with one memory read ]

> but later loops look like:

[ a loop with two reads and a write ]

> repeatedly moving the address in and out of a stack slot instead of
> keeping the value in a register.  This is not good.

Jason Merrill's ADDRESSOF optimization is supposed to take care of this;
the question is why it is not working.  That is, why on the PowerPC and
x86 do we get loops that needlessly commit the iterator to memory.

This is not just a meaningless test: standard STL code that uses
vector<T>::iterator or list<T>::iterator will generate pessimal code
because of this failure.


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