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Re: stepanov on sparc; sparc backend scheduling issues
- To: Joe Buck <jbuck at synopsys dot COM>
- Subject: Re: stepanov on sparc; sparc backend scheduling issues
- From: David Edelsohn <dje at watson dot ibm dot com>
- Date: Fri, 25 May 2001 21:28:45 -0400
- cc: mark at codesourcery dot com (Mark Mitchell), jfm2 at club-internet dot fr, gcc at gcc dot gnu dot org
Sigh. On PowerPC, the first loops look like:
._Z10accumulateIPddET0_T_S2_S1_:
LFB..18:
cmpw 0,3,4
beqlr- 0
L..218:
mr 9,3
addi 3,3,8
lfd 0,0(9)
cmpw 0,3,4
fadd 1,1,0
bne+ 0,L..218
blr
but later loops look like:
._Z10accumulateI14double_pointerdET0_T_S2_S1_:
LFB..20:
mr 0,3
stw 3,24(1)
cmpw 0,0,4
beqlr- 0
L..236:
lwz 9,24(1)
addi 0,9,8
lfd 0,0(9)
cmpw 0,0,4
stw 0,24(1)
fadd 1,1,0
bne+ 0,L..236
blr
repeatedly moving the address in and out of a stack slot instead of
keeping the value in a register. This is not good.
David