=?big5?b?pl6rSKFHIFJlOiBHQ0MgZm9yIE1pY3JvIENvbnRyb2xsZXI=?=

[tim_ouyang at sunplus dot com dot tw]

On 2001/04/13 02:56:57 AM Toshi Morita'wrote:

> >Hi!
>
> You may want to send your mail as standard text, because
> most Unixy mail readerse print out something like this
> when displaying your message:
>
> [Charset iso-2022-jp unsupported, skipping...]
> [Use 'v' to view or save this part.]
>

I am sorry. I forget to change the Notes mail's setting.

> >I am planning to port GCC for 6502. After some survey, I've found Dave
> >McWherter's port and will use it as a base to add more specific supports
> >for 6502.
> >
> >In micro controllers such as 6502, there are mechanisms like banked
memory
> >to extend the memory space. And there is zero page memory, which is
faster
> >than normal memory. Is there any port of GCC that can support features
like
> >these?
>
> Your statements are slightly incorrect, and I'm worried you don't
understand
> the 6502 architecture.
>
> Zero page on the 6502 isn't a special area of memory which is "faster
than
> normal memory". It is a part of regular memory which can be addressed by
> shorter instructions (2 bytes vs 3 bytes) which execute faster because
they
> require fewer opcode fetches.
>
> You can also access the zero page via absolute addressing as well.

   The code size is a very critical issue in our applications. The assembly
   codes generated by GCC should be near the quality of hand written
   assembly codes. Or, at least, comparable to commercial 6502 C compilers,
   say IAR’s. (IAR’s 6502 C compiler supports C language extensions to put
   variables in zero page memory.)

> Also, the 6502 has no built-in banked memory support. This is provided by
> external logic and is dependent on the external hardware.

IAR's compiler supports banked memory too. So I have to support it.

> As far as I know, there are no ports which provide support for
architectural
> features (aberrations?) similar to these.
>
> I haven't ported GCC to a new architecture myself, so the following
details
> are purely speculation:
>
> The 6502 architecture really isn't suited well for GCC. The moves between
> registers and memory are non-orthogonal and have arbitrary constraints.
>
> So, you probably want to fake a RISC-type machine which has 8 16-bit
registers
> prior to reload, and then post-reload you can split the insns into
something
> closer to the native 6502 insns.
>
> Also, you may want to pretend to have 8-bit displacement + register
indirect
> addressing modes, which you can convert post-reload into ldy #x, lda
(zp),y
> sequences.
>
> Toshi
>

Thank you for your advice.

Tim Ouyang (歐陽士庭)
IP Design Department
Intellectual Property Development Division
Sunplus Technology Co., Ltd.
19, Innovation Road 1, Science-Based Industrial Park, Hsin-Chu, Taiwan

Phone: +886-3-5786005 Ext. 2467
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