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Re: SuperH: -m4-nofpu flag
Alexandre Oliva wrote:
> Well, the ISA of a FPU-less SH4 is pretty much the same as that of
> SH3. I believe that's the reason to define __sh3__. When you need to
> tell whether it's an FPU-less SH4 or an SH3, there's __SH4_NOFPU__.
OK, I guessed (wished) that it may be the bug, but it seems not.
My concerns are cache line size and scheduling of the instruction.
For those, GCC with -m4-nofpu emits the code like SH-4 (32-byte cache
line, and dual issues), the difference between -m4 is just about FPU.
Therefore, (for me) it's natural if __SH4__ is defined instead of
__sh3__. If so, we can distingush SH-3/SH-4 by __sh3__ or __SH4__.
Actually, in Linux, we have the code like this:
------------------
#ifndef __ASM_SH_CACHE_H
#define __ASM_SH_CACHE_H
/* bytes per L1 cache line */
#if defined(__sh3__)
#define L1_CACHE_BYTES 16
#elif defined(__SH4__)
#define L1_CACHE_BYTES 32
#endif
#endif /* __ASM_SH_CACHE_H */
------------------
If we use sh-elf specs, this should be:
------------------
#if defined(__SH4__) || defined(__SH4_NOFPU__)
#define L1_CACHE_BYTES 32
#elif defined(__sh3__)
#define L1_CACHE_BYTES 16
#endif
------------------
I feel it's not cool.
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