Re: ia64 scheduling

[Daniel Berlin <dberlin at cygnus dot com>]

On Thu, 28 Dec 2000, Bernd Schmidt wrote:

> On Wed, 27 Dec 2000, Brad Lucier wrote:
> >
> > gcc -O1 -fschedule-insns2 -fno-math-errno -mieee -mcpu=ev6
> 
> Try adding -frename-registers.
> 
> There are also a few things I'd like to get implemented in schedule_ebbs;
> for example we need to figure out whether memory accesses can trap or not.
> Currently we're too conservative and assume they can all trap.  The code
> that exists in sched-rgn.c is unfortunately not going to help for ia64.
> 
> 
> Bernd
> 
> 

Which would help IA64/other platforms more, better scheduling, or a new
register allocator?
I've been working on iterated register coalescing, in addition to the
SSA value numbering/Global Value Numbering pass i'm doing.
GVN is just about done, the allocator i haven't started much on. I have a 
fast bitmatrix class (which incidently, could be used to replace sbitmap 
vectors, since you can resize mine).

However, on x86, Iterated Register Coalescing is going to be a lose, 
because you'll spill *way* too much, unless you somehow take into account 
the fact that hardware register renaming is going on.
The SML/NJ guys ran into this, and I have a paper on Optimal Spilling for 
CISC processors, that would be useful for this.

The short of it is, depending on what platform we are trying to improve 
most, time might be better spent on scheduling than register allocation.

Which reminds me, for the Pentium IV, according to the optimization 
guide, we no longer should be caring about scheduling for the decoders at 
all. I wonder if this is why so many compilers have had to be modified to 
get speed gains on the P4.

--Dan