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Re: PDP10 support
- To: lars at nocrew dot org
- Subject: Re: PDP10 support
- From: Nick Ing-Simmons <nik at tiuk dot ti dot com>
- Date: Thu, 14 Sep 2000 15:45:29 +0100 (BST)
- Cc: gcc at gcc dot gnu dot org, Gerald Pfeifer <pfeifer at dbai dot tuwien dot ac dot at>, meissner at cygnus dot com, Mark Mitchell <mark at codesourcery dot com>, Joe Buck <jbuck at racerx dot synopsys dot com>
- Organization: via, but not speaking for : Texas Instruments Ltd.
- References: <Pine.BSF.email@example.com> <firstname.lastname@example.org>
- Reply-To: Nick Ing-Simmons <nik at tiuk dot ti dot com>
Lars Brinkhoff <email@example.com> writes:
>It would also be interesting to hear from the DSP folks.
Okay here is a _personal_ view as someone that has tried to ports
to various TI DSPs:
Weird addresses would have been useful for one of the ports
(actually thing was more of a micro-controller than a DSP).
Older C2X DSPs, and modern C5X which are backward compatible are
16-bit words only. As such addressing bytes was just not possible -
packing bytes means reading 16 bits and/shift/or and write 16 bits.
C3X/C4X are basically 32-bit with "some" support for messing with bytes
they also have non-IEEE 40-bit float.
C6X is byte addressed.
C8X is byte addressed.
Most of the problems with DSPs were not the format of the addressing,
- opcode squeezing which meant that which set of index registers
you could use depended on choice of base registers etc.
Reload has no support for such stuff, so you end up using a
subset of registers.
- Register allocation - GCC likes to keep a pseudo in one hard register,
but if you multiply it and then use as an index it has to move.
So you need to split into multiple pseudos then stop GCC collapsing
them back into one.
- the lack of hardware interlocks (exposed pipeline) meaning need
to insert NOPs for loads and other multi-cycle ops - as well as branches.
- VLIW scheduling. (Super scalar without harware interlocks.)
Also register allocation which depends on which "unit" operation
is scheduled for.
- Fussy details like HI*HI => SI multiply is highly optimal
so shift schemes need to be disabled - except when used
for address generation.
- Figuring out what RTL "combine" would come up with for
expressions that mapped on to DSPish things like MPY+ADD+SHIFT
so that insn patterns that matched could be written
Nick Ing-Simmons <firstname.lastname@example.org>
Via, but not speaking for: Texas Instruments Ltd.