MIPS div_trap vs. general conditional traps

[Greg McGary <greg at mcgary dot org>]

I implemented conditional traps for MIPS using the MIPS
conditional-trap machine instructions for ISA>=2 and using the MIPS
`break' instruction for ISA==1.  I posted the patch last night.

Since then, I have noticed that the MIPS div_trap also generates
TRAP_IFs, but always translates them to conditional branches to MIPS
BREAK instructions.  Is there any reason why we shouldn't use
conditional-trap machine instructions for div_trap as well, falling
back to conditional branches to BREAK only for ISA==1 ?

One reason not to do it is that operating systems might expect div
traps to come as BREAKs (EXC == 9), rather than as traps (EXC == 13).
However, since I doubt that OSes do anything other than terminate the
program that gets a div_trap, and BREAK and trap exceptions probably
both terminate just as effectively, it ought not make so much
difference.  The div_trap stuff generates `break 6' (integer divide
overflow) and `break 7' (divide by zero), so the OS probably examines
the offending instruction in order to tailor its response.  Note that
the register/register conditional-trap insns also have a code field,
but at present, gas doesn't accept it.

For backward compatibility, we could always provide a `-m' option to
force branches to BREAKs.

Another reason not to do it, and to favor branches to BREAK even for
general conditional traps is if the conditional-trap machine
instructions are serializing.  My MIPS manuals are silent on that
issue.

Comments?

Greg