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Re: SSE Support for ia32?
Has anyone taken a look at conditional moves for the PPro and above? Does
gcc generate them?
Seems like for simple cases like this it should be pretty easy to do.
var=whatever;
if (something > something_else)
var=different;
mov eax,whatever
cmp something,something_else
cmovg eax,different
mov dword[var],eax
Just curious. If the newer version of gcc supports this, it might be the
final nudge to upgrade my compiler tools.
Andy
----- Original Message -----
From: Richard Henderson <rth@cygnus.com>
To: Mike Stump <mrs@windriver.com>
Cc: <aj@suse.de>; <gcc@gcc.gnu.org>
Sent: Thursday, July 06, 2000 7:36 PM
Subject: Re: SSE Support for ia32?
> On Wed, Jul 05, 2000 at 06:59:30PM -0700, Mike Stump wrote:
> > Yes for SSE for some versions of gcc. I haven't heard of SSE2, so I
> > cannot comment on it.
>
> It's in Intel's next generation ia32 chips, currently code-named
> Willamete (sp). The primary extensions are 2 vector doubles
> (instead of 4 vector floats), as well as more integer manipulation.
>
> AFAIK, there are no current plans for implementing SSE2; but it
> doesn't sound very hard at all, once Red Hat's current SSE code
> is integrated.
>
>
> r~
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