Re: leave instruction on ppro/pII/pIII

[John Vickers <John dot Vickers at pace dot co dot uk>]

Alexander Sokolov wrote:
> 
> It seems that gcc uses leave instruction only when generating code for
> 386, amd k6 and athlon processors. On all others it uses an equivalent
> movl %ebp,%esp popl %ebp sequence. I think that using leave on ppro, pII
> and pIII could be advantageous for the following two reasons:
> 
> 1. Both leave and movl/popl are broken down to the same 3 micro-ops,
> but leave is only one byte instruction, whereas a sequence of movl/popl
> takes 3 bytes.
> 2. In the worst case when movl goes to D0, it will take 2 clocks to decode
> the movl/popl sequence, since popl is 2 micro-op instruction and can only
> be decoded in D0, whereas leave always takes one clock to decode.
> 
> It follows from the above, that using leave we can save 2 bytes of code
> and, in some cases, one clock of decoding time.
> Any comments?

Try it and measure the results.  Shouldn't be too hard to make the
compiler emit leave instructions on the other targets, and add a switch
for that.

John.