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arm.md: define insn "loadhi_predec" -- why issue ldr, not ldrh?
- To: <gcc at gcc dot gnu dot org>
- Subject: arm.md: define insn "loadhi_predec" -- why issue ldr, not ldrh?
- From: "Dmitri Makarov" <dim at windriver dot com>
- Date: Fri, 21 Apr 2000 14:08:47 -0700
- Organization: Wind River Systems
- Reply-To: "Dmitri Makarov" <dim at windriver dot com>
What is the reason behind issuing word-long loads/stores
for loading/storing halfword values in ARM backend?
from arm.md:
(define_insn "*loadhi_preinc"
[(set (match_operand:HI 3 "s_register_operand" "=r")
(mem:HI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
(match_operand:SI 2 "index_operand" "rJ"))))
(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_ARM
&& (! BYTES_BIG_ENDIAN)
&& ! TARGET_MMU_TRAPS
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& (GET_CODE (operands[2]) != REG
|| REGNO (operands[2]) != FRAME_POINTER_REGNUM)"
"ldr%?\\t%3, [%0, %2]!\\t%@ loadhi"
[(set_attr "type" "load")])
Why not "ldr%?h\\t%3, [%0, %2]!\\t%@ loadhi" ?
From this pattern LDR insn is generated, not LDRH. Is this
on purpose or this one and others alike are just omissions?