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Re: Problem with gcc on ppc? was Re: proper regw and regrw16?
- To: gcc at gcc dot gnu dot org
- Subject: Re: Problem with gcc on ppc? was Re: proper regw and regrw16?
- From: Geoff Keating <geoffk at cygnus dot com>
- Date: 24 Mar 2000 13:58:59 -0800
- References: <v03110703b5014d1a9f37@[129.100.29.243]>
"Kevin B. Hendricks" <khendricks@ivey.uwo.ca> writes:
> What is r9 being used for at 418: and 428: and why didn't the compiler
> optimization figure out how to just move things from register to register?
Because you've specified base_addr 'volatile'. So it allocates a
memory slot at 8(sp) for the variable, and then makes every load and
store that your code specifies. Your code uses base_addr twice in
regw(), so it loads twice from the memory location. It stores once to
it in the call to regw(), so it stores to the memory location. You
didn't show the code that generates the lwbrx, but I expect it does
the same thing there.
The idea behind 'volatile' is that it means that the variable is
special; for instance, a hardware clock, that can change without the
compiler's knowledge. I doubt it makes any sense to declare a
parameter variable 'volatile', and certainly not in this context.
The change to the asm macro (which I deleted) would have made the code
'better' simply because it used base_addr fewer times.
> Is this a compiler optimization "bug"?
No. It's correct behaviour.
...
static inline void regw(volatile unsigned long base_addr, unsigned long
regindex, unsigned long regdata)
{
asm volatile ("stwbrx %1,%2,%3; eieio"
: "=m" (*(volatile unsigned *)(base_addr+regindex))
: "r" (regdata), "b" (regindex), "r" (base_addr));
}
...
> >before:
> >00000400 <R128Blank>:
> > 400: 94 21 ff e0 stwu r1,-32(r1)
> > 404: 81 23 00 f8 lwz r9,248(r3)
> > 408: 80 09 00 24 lwz r0,36(r9)
> > 40c: 39 40 00 54 li r10,84
> > 410: 90 01 00 08 stw r0,8(r1)
> > 414: 81 61 00 08 lwz r11,8(r1)
> > 418: 81 21 00 08 lwz r9,8(r1)
> > 41c: 7d 6a 5c 2c lwbrx r11,r10,r11
> > 420: 7c 00 06 ac eieio
> > 424: 90 01 00 08 stw r0,8(r1)
> > 428: 81 21 00 08 lwz r9,8(r1)
> > 42c: 61 6b 04 00 ori r11,r11,1024
> > 430: 80 01 00 08 lwz r0,8(r1)
> > 434: 7d 6a 05 2c stwbrx r11,r10,r0
> > 438: 7c 00 06 ac eieio
> > 43c: 38 21 00 20 addi r1,r1,32
> > 440: 4e 80 00 20 blr
--
- Geoffrey Keating <geoffk@cygnus.com>