Re: Predicated execution

[Richard Earnshaw <rearnsha at arm dot com>]

P.E. on the ARM is very important, especially for those processors that 
don't have branch prediction or other branch acceleration techniques, or 
when optimizing for code size.  The current code in FINAL_PRESCAN_INSN is 
OK as far as it goes, but misses many possible cases because it does not 
do enough condition code analysis at code lables.

Substantially all instructions can be predicated on the single condition 
code register (there is one instruction in ARMv5 that has no predicate), 
though in a machine description, some instructions use the predicate as a 
natural part of the instruction (eg conditional branches, conditional 
moves).  An important feature of the ARM is that even instructions that 
set the condition code register can also be predicated, so we get 
interesting sequences such as

	if (a && b)
	  c++;

  which can be compiled to:

	cmp	a, #0
	cmpne	b, #0
	addne	c, #1


> In particular what is the form in RTL of your comparisons that enable
P.E.

It is a set of a single hard register (reg 24).  How predicated 
instructions should be represented is less clear -- I can think of no way 
in rtl to specify that an instruction has no side effects if its predicate 
is false, for example

	ldrne	r0, [r1, #4]!

is a post-increment word load, but the increment is not performed if the 
instruction fails its predicate.

Richard