Re: 64-bit PowerPC SCC instruction generation

[Michael Meissner <meissner at cygnus dot com>]

On Wed, Jan 05, 2000 at 02:55:31PM -0500, David Edelsohn wrote:
> 	I have been looking into how to generate 64-bit SCC instructions
> in the 64-bit PowerPC port.  The problem stems from the lack of
> mode-specific sXX pattern names.  At first I thought that I would need to
> do something complicated along the lines of mips.c:gen_int_relational(),
> but further invetigation looks like I can do something simpler in the sXX
> patterns.  Does the following style of pattern look correct?
> 
> (define_expand "seq"
>   [(set (match_dup 2) (match_dup 1))
>    (set (match_operand:SI 0 "gpc_reg_operand" "")
>         (eq:SI (match_dup 2) (const_int 0)))]
>   ""
>   "
> { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
>   operands[1] = gen_rtx_COMPARE (mode,
>                                  rs6000_compare_op0, rs6000_compare_op1);
>   operands[2] = gen_reg_rtx (mode);
> 
>   if (TARGET_POWERPC64
>       && (GET_MODE (rs6000_compare_op0) == DImode
>           || GET_MODE (rs6000_compare_op1) == DImode))
>     {
>       emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1]));
>       convert_move (operands[0],
>                     gen_rtx_EQ (DImode, operands[2], const0_rtx), 0);
>       DONE;
>     }
> }")

You should be able to change the GET_MODE tests to just look at op0, since the
compiler canonicalizes the constant to always be in the op1 position.  Also, I
don't believe that you want the mode to be SI for floating point compares in
the powerpc64 case.

> The change is adding the TARGET_POWERPC64 conditional block.
> 
> 	I am not sure whether the convert_move() actually is necessary as
> it is in the Mips code.  The rs6000 port currently does not keep track of
> the original comparison mode, as the Mips port does.  I am not sure
> whether basing the result mode on the operands' modes is better.

-- 
Michael Meissner, Cygnus Solutions
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