Re: PA casesi questions

[Jeffrey A Law <law at cygnus dot com>]

  In message <200001060451.XAA25545@jwlab.FEITH.COM>you write:
  > 
  > on hppa1.1-hp-hpux10.20 results in:
  > 
  > (note 134 2 4 [bb 0] NOTE_INSN_BASIC_BLOCK)
  > 
  > (insn 4 134 5 (set (reg/v:SI 94)
  >         (reg:SI 26 %r26)) 63 {reload_outsi+2} (nil)
  >     (expr_list:REG_EQUIV (mem/f:SI (plus:SI (reg:SI 3 %r3)
  >                 (const_int -36 [0xffffffdc])) 1)
  >         (nil)))
  > 
  > (note 5 4 8 "" NOTE_INSN_FUNCTION_BEG)
  > 
  > (note 8 5 108 0 NOTE_INSN_BLOCK_BEG)
  > 
  > (jump_insn 108 8 120 (set (pc)
  >         (if_then_else (gtu (reg/v:SI 94)
  >                 (const_int 9 [0x9]))
  >             (label_ref 113)
  >             (pc))) 47 {bleu+1} (nil)
  >     (nil))
  > 
  > (note 120 108 109 [bb 1] NOTE_INSN_BASIC_BLOCK)
  > 
  > (jump_insn 109 120 110 (set (pc)
  >         (plus:SI (mem:SI (plus:SI (pc)
  >                     (reg/v:SI 94)) 0)
  >             (label_ref 110))) 284 {casesi0} (nil)
  >     (nil))
  > 
  > (code_label 110 109 111 15 "" "" [num uses: 1])
  > 
  > (jump_insn 111 110 112 (addr_vec:DI[ 
  >             (label_ref:SI 13)
  >             (label_ref:SI 21)
  >             (label_ref:SI 30)
  >             (label_ref:SI 39)
  >             (label_ref:SI 48)
  >             (label_ref:SI 57)
  >             (label_ref:SI 66)
  >             (label_ref:SI 75)
  >             (label_ref:SI 84)
  >             (label_ref:SI 93)
  >         ] ) -1 (nil)
  >     (nil))
  > 
  > (barrier 112 111 10)
  > 
  > which doesn't look right.  Specifically:
  > 
  >   1) Jump_insn 109 looks like it does a jump relative to code_label 110,
  >      however an addr_vec is being used, not an addr_diff_vec.  Should
  >      CASE_VECTOR_PC_RELATIVE be defined in pa.h and ASM_OUTPUT_ADDR_VEC_ELT
  >      omitted?
Not an issue.  Switches in PA-land turn into an indirect branch (insn 108)
which jumps to a direct branch to the ultimate destination (insn 111).

ie if we assume the index is in %r1 we'll generate something like

	[ normalize index]
	blr %r1,%r0  insn 108
	nop

	b case 1    insn 111, index 0
	nop	
	b case 2    insn 111, index 1
	nop
	b case 3    insn 111, index 2
	nop
	[ ... ]

The blr will jump to the appropriate "b case X" instruction, which in turn
jumps to the ultimate target.

  >   2) The addr_vec is DImode, jump_insn 109 references the memory in SImode,
  >      and judging by jump_insn 108 register 94 is an index into a QImode
  >      jump table.  Should the casesi jump (assuming that TARGET_BIG_SWITCH
  >      isn't set) read:
  > 
  >      (set (pc) (plus:SI (sign_extend:SI (mem:QI (plus:SI (pc)
  >                     (reg/v:SI 94)) 0))
  >             (label_ref 110)))
  > 
  >      and CASE_VECTOR_MODE changed appropriately?
No, the code as it stands is correct.

The mode of the ADDR_VEC/ADDR_DIFF_VEC indicates the size (in bytes) of each
item in the jump vector.  Since each entry in the jump vector corresponds to
exactly 2 instructions (8 bytes) the mode of the ADDR_DIFF should be DImode.



  >   3) Actually as a minor style issue perhaps:
  > 
  >      (set (pc) (plus:SI (sign_extend:SI (mem:QI (plus:SI (label_ref 110)
  >                     (reg/v:SI 94)) 0))
  >             (pc)))
  > 
  >      is better.
Possibly.

I've actually got a rewrite of that code to make it more branch prediction
friendly for the PA8000 series machines, but it doesn't work yet.  :(  

jeff