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Re: 64-bit PowerPC SCC instruction generation
- To: Geoff Keating <geoffk at cygnus dot com>
- Subject: Re: 64-bit PowerPC SCC instruction generation
- From: David Edelsohn <dje at watson dot ibm dot com>
- Date: Wed, 05 Jan 2000 16:48:24 -0500
- cc: law at cygnus dot com, meissner at cygnus dot com, gcc at gcc dot gnu dot org
>>>>> Geoff Keating writes:
Geoff> I would put a mode in the gen_rtx_SET ('mode' looks like the right
Geoff> one) rather than VOIDmode.
I used VOIDmode because that is the mode that the gen_rtx_SET
generated in emit-insn.c uses.
Geoff> The convert_move probably is necessary, if you still want operand[0]
Geoff> to have SImode. I suspect you really want operand[0] to have DImode,
Geoff> in which case the match_operand needs to be changed, and you can do:
Geoff> Perhaps if this is done then the predicate should double-check that
Geoff> the mode of its operand is the register-size mode?
The comments in mips.c or gen_int_relational() imply that the mode
is required in the pattern:
These patterns are called with a target in the mode of
the Scond instruction pattern. Since this must be a constant, we
must use SImode. This means that if RESULT is non-zero, it will
always be an SImode register, even if TARGET_64BIT is true.
This implies that the convert_move is necessary.
David