I need a GCC porting hint (or two) for an odd architecture...

[Andrew Webber <andreww at videologic dot com>]

I might be off topic for this list for these questions...

I have been playing around with porting gcc to an odd architecture.  The
architecture is odd for a number of reasons, however, of most relevance
to my questions are memory operations.

In this architecture simple memory reads are actually made up of two
machine instructions - one to issue the read address and one to pick up
the read data.  I have made a machine description that uses a define
expand to split memory operations in the two parts but have come across
a problem when optimization is turned on as the first of my two
instructions gets optimized out (just before .c.flow is written out).  I
could issue the two instructions as assembly together, however, I wanted
to try going through RTL to see if I could use function units or
whatever to reschedule these instructions to reduce stalling for memory
reads.

In addition, my odd architecture consists of two groups of registers
where for a memory write one group can be used for the write address and
one for the write data - is there any pleasant way to communicate this
to gcc (I currently use the inelegant solution of crippling the machine
description to only allow write addresses from one group and write data
from the other).

Thanks,

Andrew.