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Re: HARD_REGNO_MODE_OK on PA-RISC (revisited)
- To: law@cygnus.com
- Subject: Re: HARD_REGNO_MODE_OK on PA-RISC (revisited)
- From: Mark Klein <mklein@dis.com>
- Date: Tue, 24 Aug 1999 21:56:31 -0700
- Cc: gcc@gcc.gnu.org
- References: <Your message of Mon, 19 Apr 1999 10:28:21 PDT. <4.1.19990419075711.00b03d90@garfield.dis.com>
At 08:37 PM 8/24/99 -0600, Jeffrey A Law wrote:
>There is nothing wrong with requiring aligned registers, it is just
suboptimal.
The original question had to do with long double which according to the ACD
must be aligned on a 128 bit boundary. This is what works for long double.
If I'm missing something else, please refresh my memory, as it has been
over four months since I looked at this.
/*
* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
* 32 bit reg/subreg can fit in any general register. On PA1.0, FP regs
* are 64 bits wide, but 32 bit quantities must be in the leftmost 32
* bits of the FP register. On PA1.1, FP regs are still 64 bits wide,
* but both halves can contain 32 bit quantities. In gcc, these registers
* are each treated as a separate 32 bit FP register. So, modes greater
* than 32 bits must be aligned on "even" registers. 128 bit floating
* point must be aligned in evenly aligned FP registers on PA 1.0 and
* because of the remapping for PA1.1, registers evenly divisible by 4.
* For PA 1.0, disallow wide non-floating point modes in FP registers.
*/
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) == 0 \
? (MODE) == CCmode || (MODE) == CCFPmode \
: FP_REGNO_P (REGNO) \
? !TARGET_PA_11 \
? GET_MODE_SIZE (MODE) <= 4 || \
GET_MODE_CLASS (MODE) == MODE_FLOAT && \
(GET_MODE_SIZE (MODE) <= 8 && ((REGNO) & 1) == 0 || \
((REGNO) & 3) == 0) \
: GET_MODE_SIZE (MODE) <= 4 || \
(GET_MODE_SIZE (MODE) <= 8 && ((REGNO) & 1) == 0) || \
((REGNO) & 3) == 0 \
: 1)
--
Mark Klein DIS International, Ltd.
http://www.dis.com 415-892-8400
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