Re: PA8000 performance oddity

["Geert Bosch" <bosch at gnat dot com>]

On Tue, 25 May 1999 11:41:57 -0400, Jerry Quinn wrote:

  It almost suggested that there is some kind of cache effect inside the
  processor favoring recently used registers over ones that are idle.  Is
  this possible/reasonable?  If so, it would make correct machine modeling
  much more complex.

This could well be possible. At least on Intel Pentium II, referencing
register names that are still in use by a non-retired intruction
can be faster than using new register names. The issue here is
mapping the register names to actual (renamed) registers.

Favoring new renamings of already used register names over
using more register names may also reduce register pressure.

Compare the schedules below for the following program fragment:

Mem2 := Mem1 * Mem1;
Mem4 := Mem3 + 1;

  Schedule 1)       Schedule 2)

1 rA := Mem1;       rA := Mem1;
2 rB := Mem3;       rA := rA * rA;
3 rA := rA * rA;    Mem2 := rA;
4 rB := rB + 1;     rA := Mem3;
5 Mem2 := rA;       rA := rA + 1;
6 Mem4 := rB;       Mem4 := rA;

In 1) we use two register names, and 4 register instances.
On the other hand in 2) we only use a single name, still
with 4 instances. It is interesting to look at the effects
of out of order execution on this schedule. It may be that
schedule 2) performs as good as 1) while using less register
names.

Lets assume a machine that issues 1 instruction per cycle, has one
unit that can read, two for arithmetic and two for write. Read and
Write have a latency of three cycles, Add 1 and Mult 5.

  Execution 1)     Execution 2)

1 Read           1 Read
  |   2 Read       |
  |     :          |
3 Mult  |        2 Mult 4 Read
  |     |          |      |
  |   4 Add        |      |
  |   5 Write      |    5 Add
  |     |          |    6 Write
6 Write |        3 Write  |
  |     *          |      |
  |                |      *
  *                *

Regards,
   Geert