HARD_REGNO_MODE_OK on PA-RISC (revisited)

[Mark Klein <mklein at dis dot com>]

A while back we had a discussion about how I feel HARD_REGNO_MODE_OK is wrong.
We never resolved it back then, so I'd like to try again.

Facts:

PA1.0
32 general registers, each 32 bits.
16 floating pointer registers, each 64 bits. 32 bit FP values can only be
in the
left half of a 64 bit FP register. Registers are numbered 0..15.
128 bit FP must be aligned on an even register boundary.

PA1.1
32 general registers, each 32 bits.
32 floating point registers, each 64 bits. Each half of the register may
contain
and operate on 32 bit FP values. Registers are numbered 0..31. Left and right
half are indicated by appending an "L" or "R" to the register name (e.g.
%fr4L).
128 bit FP must be aligned on an even register boundary.

A general register may hold any reg/subreg of 32 bits in any alignment.

Here's the current HARD_REGNO_MODE_OK:

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   On the HP-PA, the cpu registers can hold any mode.  We 
   force this to be an even register is it cannot hold the full mode.  */ 
#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 
  ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode                \
   /* On 1.0 machines, don't allow wide non-fp modes in fp regs. */     \
   : !TARGET_PA11 && FP_REGNO_P (REGNO)                         \
     ? GET_MODE_SIZE (MODE) <= 4 || GET_MODE_CLASS (MODE) == MODE_FLOAT \
   /* Make wide modes be in aligned registers. */                       \
   : GET_MODE_SIZE (MODE) <= 4 || ((REGNO) & 1) == 0)

(Please note that the register mapping for gcc FP is such that the even
registers
are the left half of the FP register. So, pseudo register 32 is hardware
register
%fr4. Pseudo register 33 is hardware register %fr4R, 34 is %fr5 and 35 is
%fr5R,
etc.)

I believe the macro is wrong because it forces even register alignment for
larger
modes in the general register file as well as the FP registers. Calling
conventions do provide for certain register alignment in the general register
file, but only in the argument registers, and that's handled by another macro.

In addition, it will need to change for long double support that in TFMODE,
the FP pseudo registers must be evenly divisible by 4.

Here's what I propose:

/*
 * Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
 * 32 bit reg/subreg can fit in any general register. On PA1.0, FP regs
 * are 64 bits wide, but 32 bit quantities must be in the leftmost 32
 * bits of the FP register. On PA1.1, FP regs are still 64 bits wide,
 * but both halves can contain 32 bit quantities. In gcc, these registers
 * are each treated as a separate 32 bit FP register. Modes greater
 * than 32 bits must be aligned on even registers. 128 bit floating
 * point must be aligned in evenly aligned FP registers on PA 1.0 and
 * because of the remapping for PA1.1, registers evenly divisible by 4.
 * For PA 1.0, disallow wide non-floating point modes in FP registers.
 */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
  ((REGNO) == 0                                                         \
    ? (MODE) == CCmode || (MODE) == CCFPmode                            \
    : FP_REGNO_P (REGNO)                                                \
       ? !TARGET_PA11                                                   \
          ? GET_MODE_SIZE (MODE) <= 4 ||                                \
            GET_MODE_CLASS (MODE) == MODE_FLOAT &&                      \
            (GET_MODE_SIZE (MODE) <= 8 && ((REGNO) & 1) == 0 ||         \ 
            ((REGNO) & 3) == 0)                                         \
          : GET_MODE_SIZE (MODE) <= 4  ||                               \
            (GET_MODE_SIZE (MODE) <= 8 && ((REGNO) & 1) == 0) ||        \
            ((REGNO) & 3) == 0                                          \
       : 1)
--
Mark Klein                                 DIS International, Ltd.
http://www.dis.com                         415-892-8400
PGP Public Key Available