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Re: comments on loop changes
- To: Michael Hayes <m dot hayes at elec dot canterbury dot ac dot nz>
- Subject: Re: comments on loop changes
- From: Michael Hayes <m dot hayes at elec dot canterbury dot ac dot nz>
- Date: Sat, 06 Feb 1999 11:35:44 +1300 (NZDT)
- Cc: Richard Henderson <rth at cygnus dot com>, Jorn Wolfgang Rennecke <amylaar at cygnus dot com>, egcs at cygnus dot com
- References: <19990131145827.A17537@cygnus.com><14004.58794.114591.617460@ongaonga.elec.canterbury.ac.nz><19990131171622.B17567@cygnus.com><14005.526.838270.939987@ongaonga.elec.canterbury.ac.nz><19990131214105.A17739@cygnus.com><14005.30140.529348.966766@ongaonga.elec.canterbury.ac.nz><19990201025925.A17750@cygnus.com><14008.51524.336200.906670@ongaonga.elec.canterbury.ac.nz>
Michael Hayes writes:
> I've found I can emulate the behaviour of the Sparc by setting
> ADDRESS_COST to 1. I then get essentially the same pattern of GIVs
> and the GIV combination works well.
With the Sparc we get the following expressions which the giv combiner
does the right thing:
ra = biv * 8
*(ra + rb)
*(ra + rc)
rd = ra + rb
re = ra + rc
*(rd + 4)
*(re + 4)
However, if a reg+reg addressing cost is higher than a reg addressing
cost (as on the c4x), CSE turns the above into:
ra = biv * 8
rd = ra + rb
re = ra + rc
*rd
*re
*(rd + 4)
*(re + 4)
Unfortunately, giv combination does the wrong thing with this.
The upshot is, if the address costs try to discourage reg+reg
addressing modes, there is a greater chance of generating them!
Michael.