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Re: missed optimization, would be very helpful



  In message <199901011852.NAA07301@rabi.phys.columbia.edu>you write:
  > On Thu, 31 Dec 1998 23:03:25 -0400, Horst von Brand wrote:
  > >Zack Weinberg <zack@rabi.columbia.edu> said:
  > >> In a loop of the form
  > >> 
  > >> while (condition) (*int_ptr)++;
  > >> 
  > >> gcc generates a read-mod-write cycle to the memory location *int_ptr at 
  > each
  > >> iteration of the loop.
  > 
  > >
  > >It's still there with egcs-19981226. On i586:
  > >
  > 
  > This is what I see too.  rth doesn't get that on Alpha, so it's an i386.md
  > problem at this point.  A guess at a kludge: if the incdi pattern were
  > changed to not allow memory operands, that might force the optimization. 
  > But that's overkill.
I think this is another example of how we want to do post-reload instruction
splitting for the x86.

If we can find a scratch register after reload, then we can turn the
read-mod-write cycle into a read, increment, write as 3 instructions with
better scheduling opportunities.

That way we get the benefit of better scheduling/pairing without adding
register pressure to the port and causing spills.

We've got a lot of the infrastructure in the compiler now -- most importantly
the post-reload life analysis pass.  It's just waiting for someone to take
up the task.

jeff


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