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Re: K6 and decoding bottleneck
- To: hubicka at atrey dot karlin dot mff dot cuni dot cz
- Subject: Re: K6 and decoding bottleneck
- From: John Wehle <john at feith dot com>
- Date: Wed, 11 Nov 1998 18:13:52 -0500 (EST)
- Cc: egcs at cygnus dot com
> At the other hand it shows, that decoder optimization strategies seems to
> be significant for K6 and maybe for PentiumPro too. The decoding seems
> to be main bottleneck of K6 (don't know about PPro, because it can decode
> three instructions at cycle but execute only two as far as I can remember)
Intel recommends scheduling for the instruction decoder on the PPro /
Pentium II in addition to scheduling for the execution units. The i386
scheduling changes I played in January attempted to do this and it did
seem to help.
-- John
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