Re: Possible CSE quirk involving SUBREG on the i386

[Jeffrey A Law <law at cygnus dot com>]

  In message <199807010318.UAA26631@dm.cobaltmicro.com>you write:
  > Right, my current theory is that combine likes to look at things "3 at
  > a time" to determine candidates.  For some of the cases I was trying
  > to get to work, it would need to look at things "4 at a time".
Yup.  Combine looks at insns in groups of 2 or 3.

You can make it look at larger groups by making intermediate patterns.

Here's an example from the H8 port:

;; This is a "bridge" instruction.  Combine can't cram enough insns
;; together to crate a MAC instruction directly, but it can create
;; this instruction, which then allows combine to create the real
;; MAC insn.
;;
;; Unfortunately, if combine doesn't create a MAC instruction, this
;; insn must generate reasonably correct code.  Egad.
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=a")
        (mult:SI
          (sign_extend:SI
            (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
          (sign_extend:SI
            (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
)]
  "TARGET_H8300S"
  "clrmac\;mac  %2,%1"
  [(set_attr "length" "6")
   (set_attr "cc" "none_0hit")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=a")
        (plus (mult:SI
          (sign_extend:SI (mem:HI
            (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
          (sign_extend:SI (mem:HI
            (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
              (match_operand:SI 3 "register_operand" "0")))]
  "TARGET_H8300S"
  "mac  %2,%1"