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Fwd: Question on parallel execution inside the processor


In a message dated 6/23/98 1:47:36 PM Pacific Daylight Time,
martin.kahlert@mchp.siemens.de writes:

> Is there any part of gcc, which tries to take advantage
>  of parallel execution inside the processor

I believe that's one reason the MIPS port doesn't support gas.  The MIPS
assembler generally achieves 70% of the performance of a native compiler when
used with egcs on R10K, which is getting a boost both from the assembler and
from the hardware out-of-order execution.  There's a cost, of course-- no gdb,
considerable loss of profiling information.



Hi,
is there any pass in egcs, which tries to schedule instructions
in a way, that no pipeline stalls occur any more?

The haifa scheduler optimizes on RTL code - doesn't it?
So it can't know anything about assembler instructions,
which can only be executed in pipeline X and therefor 
shouldn't be preceeded by instructions which only
work in X, too. A good compiler would try to put
instructions in between.

So the question is:
Is there any part of gcc, which tries to take advantage
of parallel execution inside the processor and if the answer
was yes, where does it get its info about that from?

Thanks for any help,
Martin.



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