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Question on parallel execution inside the processor
- To: egcs at cygnus dot com
- Subject: Question on parallel execution inside the processor
- From: Martin Kahlert <martin dot kahlert at mchp dot siemens dot de>
- Date: Tue, 23 Jun 1998 15:29:48 +0200
Hi,
is there any pass in egcs, which tries to schedule instructions
in a way, that no pipeline stalls occur any more?
The haifa scheduler optimizes on RTL code - doesn't it?
So it can't know anything about assembler instructions,
which can only be executed in pipeline X and therefor
shouldn't be preceeded by instructions which only
work in X, too. A good compiler would try to put
instructions in between.
So the question is:
Is there any part of gcc, which tries to take advantage
of parallel execution inside the processor and if the answer
was yes, where does it get its info about that from?
Thanks for any help,
Martin.