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Re: Alpha divsi3, modsi3, udivsi3, umodsi3
- To: Torbjorn Granlund <tege at matematik dot su dot se>, Richard Henderson <rth at cygnus dot com>
- Subject: Re: Alpha divsi3, modsi3, udivsi3, umodsi3
- From: Richard Henderson <rth at cygnus dot com>
- Date: Tue, 2 Jun 1998 14:10:54 -0700
- Cc: egcs at cygnus dot com
- References: <19980602093911.A19195@dot.cygnus.com> <199806021638.SAA31963@tiger.matematik.su.se>
- Reply-To: Richard Henderson <rth at cygnus dot com>
On Tue, Jun 02, 1998 at 06:38:10PM +0200, Torbjorn Granlund wrote:
> I'd suggest that we simply emit the sign extends using define_expand for
> these patterns. In some cases, combine or cse will be able to remove these;
> but having them there in some unneeded situations is still better than
> calling the 64-bit variants...!
Indeed. I know, for example, that the Linux divl converges 3 times
faster on average than divq because it need not consider overflow.
Yet somehow it had escaped my attention that gcc was not generating
these calls.
I will be applying the following patch.
r~
Tue Jun 2 14:02:38 1998 Richard Henderson <rth@cygnus.com>
* alpha.md (divsi3, udivsi3, modsi3, umodsi3): Enable, and work
around an OSF/1 library bug wrt sign-extension of inputs.
Index: gcc/config/alpha/alpha.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.38
diff -c -p -d -r1.38 alpha.md
*** alpha.md 1998/05/11 08:31:20 1.38
--- alpha.md 1998/06/02 20:56:26
***************
*** 804,864 ****
;; The divide and remainder operations always take their inputs from
;; r24 and r25, put their output in r27, and clobber r23 and r28.
! ;; ??? comment out the divsi routines since the library functions
! ;; don't seem to do the right thing with the high 32-bits of a
! ;; register nonzero.
! ;(define_expand "divsi3"
! ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
! ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
! ; (parallel [(set (reg:SI 27)
! ; (div:SI (reg:SI 24)
! ; (reg:SI 25)))
! ; (clobber (reg:DI 23))
! ; (clobber (reg:DI 28))])
! ; (set (match_operand:SI 0 "general_operand" "")
! ; (reg:SI 27))]
! ; "!TARGET_OPEN_VMS"
! ; "")
! ;(define_expand "udivsi3"
! ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
! ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
! ; (parallel [(set (reg:SI 27)
! ; (udiv:SI (reg:SI 24)
! ; (reg:SI 25)))
! ; (clobber (reg:DI 23))
! ; (clobber (reg:DI 28))])
! ; (set (match_operand:SI 0 "general_operand" "")
! ; (reg:SI 27))]
! ; "!TARGET_OPEN_VMS"
! ; "")
! ;(define_expand "modsi3"
! ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
! ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
! ; (parallel [(set (reg:SI 27)
! ; (mod:SI (reg:SI 24)
! ; (reg:SI 25)))
! ; (clobber (reg:DI 23))
! ; (clobber (reg:DI 28))])
! ; (set (match_operand:SI 0 "general_operand" "")
! ; (reg:SI 27))]
! ; "!TARGET_OPEN_VMS"
! ; "")
! ;(define_expand "umodsi3"
! ; [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
! ; (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
! ; (parallel [(set (reg:SI 27)
! ; (umod:SI (reg:SI 24)
! ; (reg:SI 25)))
! ; (clobber (reg:DI 23))
! ; (clobber (reg:DI 28))])
! ; (set (match_operand:SI 0 "general_operand" "")
! ; (reg:SI 27))]
! ; "!TARGET_OPEN_VMS"
! ; "")
(define_expand "divdi3"
[(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
--- 804,861 ----
;; The divide and remainder operations always take their inputs from
;; r24 and r25, put their output in r27, and clobber r23 and r28.
! ;; ??? Force sign-extension here because some versions of OSF/1 don't
! ;; do the right thing if the inputs are not properly sign-extended.
! ;; But Linux, for instance, does not have this problem. Is it worth
! ;; the complication here to eliminate the sign extension?
! (define_expand "divsi3"
! [(set (reg:DI 24) (sign_extend:DI (match_operand:SI 1 "input_operand" "")))
! (set (reg:DI 25) (sign_extend:DI (match_operand:SI 2 "input_operand" "")))
! (parallel [(set (reg:DI 27)
! (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
! (clobber (reg:DI 23))
! (clobber (reg:DI 28))])
! (set (match_operand:SI 0 "general_operand" "")
! (subreg:SI (reg:DI 27) 0))]
! "!TARGET_OPEN_VMS"
! "")
! (define_expand "udivsi3"
! [(set (reg:DI 24) (sign_extend:DI (match_operand:SI 1 "input_operand" "")))
! (set (reg:DI 25) (sign_extend:DI (match_operand:SI 2 "input_operand" "")))
! (parallel [(set (reg:DI 27)
! (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
! (clobber (reg:DI 23))
! (clobber (reg:DI 28))])
! (set (match_operand:SI 0 "general_operand" "")
! (subreg:SI (reg:DI 27) 0))]
! "!TARGET_OPEN_VMS"
! "")
! (define_expand "modsi3"
! [(set (reg:DI 24) (sign_extend:DI (match_operand:SI 1 "input_operand" "")))
! (set (reg:DI 25) (sign_extend:DI (match_operand:SI 2 "input_operand" "")))
! (parallel [(set (reg:DI 27)
! (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
! (clobber (reg:DI 23))
! (clobber (reg:DI 28))])
! (set (match_operand:SI 0 "general_operand" "")
! (subreg:SI (reg:DI 27) 0))]
! "!TARGET_OPEN_VMS"
! "")
! (define_expand "umodsi3"
! [(set (reg:DI 24) (sign_extend:DI (match_operand:SI 1 "input_operand" "")))
! (set (reg:DI 25) (sign_extend:DI (match_operand:SI 2 "input_operand" "")))
! (parallel [(set (reg:DI 27)
! (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
! (clobber (reg:DI 23))
! (clobber (reg:DI 28))])
! (set (match_operand:SI 0 "general_operand" "")
! (subreg:SI (reg:DI 27) 0))]
! "!TARGET_OPEN_VMS"
! "")
(define_expand "divdi3"
[(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
***************
*** 912,926 ****
"!TARGET_OPEN_VMS"
"")
! ;(define_insn ""
! ; [(set (reg:SI 27)
! ; (match_operator:SI 1 "divmod_operator"
! ; [(reg:SI 24) (reg:SI 25)]))
! ; (clobber (reg:DI 23))
! ; (clobber (reg:DI 28))]
! ; "!TARGET_OPEN_VMS"
! ; "%E1 $24,$25,$27"
! ; [(set_attr "type" "jsr")])
(define_insn ""
[(set (reg:DI 27)
--- 909,923 ----
"!TARGET_OPEN_VMS"
"")
! (define_insn ""
! [(set (reg:DI 27)
! (sign_extend:DI (match_operator:SI 1 "divmod_operator"
! [(reg:DI 24) (reg:DI 25)])))
! (clobber (reg:DI 23))
! (clobber (reg:DI 28))]
! "!TARGET_OPEN_VMS"
! "%E1 $24,$25,$27"
! [(set_attr "type" "jsr")])
(define_insn ""
[(set (reg:DI 27)