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Re: alpha failure on 920810-1
- To: wilson at cygnus dot com (Jim Wilson)
- Subject: Re: alpha failure on 920810-1
- From: Joern Rennecke <amylaar at cygnus dot co dot uk>
- Date: Wed, 29 Apr 1998 22:13:05 +0100 (BST)
- Cc: rth at cygnus dot com, egcs at cygnus dot com
> The reason is that the limited comparison
> done by the conditional move does not follow all of the IEEE rules
> that the comparision insn does, but rather simply test that the
> register has no bits set.
...
> To fix this elegantly, we need to make the RTL operations distinct if
> they are performing different operations. Since we can't do this with
> CCmodes, it seems to imply that we need new comparison operators. For
> instance, perhaps we need eqieee separate from eq, similar to how gtu is
> separate from gt. This would require changing a lot of code though to
> handle the new operators though. That would be a major task.
>
> Adding a strategic unspec operation could fix the problem, at the expense
> of uglifying the alpha.md file a bit, and perhaps losing some optimizations.
> It is likely a simpler solution though.
If it tests only if all bits are zero, I think we should express this
as a DImode equality test to zero:
(set (reg:DF 1)
(eq:DF (reg:DF 2) (reg:DF 3)))
(set (reg:DF 4)
(if_then_else:DF (eq (subreg:DI (reg:DF 1) 0)
(const_int 0))
(reg:DF 5)
(reg:DF 4)))