Re: andcc & gcc64

[Richard Henderson <rth at cygnus dot com>]

[ Forwarding to the egcs list for other ideas. ]

I'm not sure how to go about fixing this kind of thing, since
I don't know where it would get decided not to use CC in favour
of a register.

You might be able to add a peephole to change to 

	andcc reg, 1024, reg
 	be,pn %[xi]cc, xx

assuming CC is not live.  I don't know if this really recovers
the lost speed...


r~


On Tue, Jan 20, 1998 at 05:35:14PM +0100, Jakub Jelinek wrote:
> Hi!
> 
> While looking at resulting kernel code from both ss9706xx and egcs, I found
> out that stuff like
> if (x & 1024) {
> }
> 
> is done very badly for -m64, it usually turns into
> 
> 	and reg, 1024, reg
> 	brz,pn reg, xx
> 
> which is very very bad performance wise (and the kernel is full of that).
> Doing 
> 	andcc reg, 1024, %g0
> 	be,pn %[xi]cc, xx
> 
> would be much better.
> But I don't know where exactly to look into. There is a change from
> and + set cc into cmp_zero_extract in combine, but apparently during RTL
> generation, gcc decides not use cc at all and test a register. Combiner
> doesn't convert it then. Richard, do you have any ideas how to optimize
> that? It is desirable to avoid using cc as much as possible, but gcc would
> need some prediction on how often will be cc used. Or do you think it is
> doable in some later pass to convert a sequence of and, testreg for
> nonzero into andcc if CC can be clobered? Which pass could that be and how
> could it be done without touching generic files?
> 
> Cheers,
>     Jakub
> ___________________________________________________________________
> Jakub Jelinek | jj@sunsite.mff.cuni.cz | http://sunsite.mff.cuni.cz
> Administrator of SunSITE Czech Republic, MFF, Charles University
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