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Re: base + index register addressing
- To: law at cygnus dot com
- Subject: Re: base + index register addressing
- From: "Michael P. Hayes" <michaelh at ongaonga dot chch dot cri dot nz>
- Date: Sat, 18 Oct 1997 12:39:26 +1300
- Cc: meissner at cygnus dot com, michaelh at ongaonga dot chch dot cri dot nz, egcs at cygnus dot com, gcc2 at cygnus dot com
- References: <199710171559.LAA25330@tweedledumb.cygnus.com><11680.877104611@hurl.cygnus.com>
Jeffrey A Law writes:
> > I was going to comment that the patch might be even better, if it
> > dealt with register + scaled register that some machines have (such
> > as the x86, ns32k, 88k to name the ones I've dealt with).
> It's worth noting that patch only helps when the base/index is a hard reg,
> which limits its usefulness on most of our platforms. It's unclear if
> the benefit for handling scaled register would outweigh the work involved.
Most of the utility of the patch occurs when an incoming function
argument is in a hard base (or possibly index) register.
IMO, things would be simpler if two register addresses were
canonicalized so that the base register preceeded the index register,
i.e., (mem (plus (base_reg) (index_reg)). This would reduce the
ambiguity when it comes to allocating base and index registers.
mph...