This is the mail archive of the gcc-regression@gcc.gnu.org mailing list for the GCC project.
| Index Nav: | [Date Index] [Subject Index] [Author Index] [Thread Index] | |
|---|---|---|
| Message Nav: | [Date Prev] [Date Next] | [Thread Prev] [Thread Next] |
| Other format: | [Raw text] | |
The new failures are: native gcc.sum gcc.c-torture/execute/960512-1.cThis is a big mess. This latent bug was introduced by: * config/rs6000/rs6000.md: Add missing int register target case to movdf_low.
I needed to lay down for a minute to get an idea which seems to fix this testcase (and should fix others which could have came up).
But basically instead of emitting the following sequence for the load: addis r2,r31,ha16(LC0-"L00000000001$pb") --- lwz r3,lo16(LC0-"L00000000001$pb")(r2) addis r4,r31,ha16(LC0-"L00000000001$pb"+4) lwz r4,lo16(LC0-"L00000000001$pb"+4)(r4)
Where --- was the load for r31 had already happened. We should emit: addis r2,r31,ha16(LC0-"L00000000001$pb") --- lwz r3,lo16(LC0-"L00000000001$pb")(r2) la r4,lo16(LC0-"L00000000001$pb")(r2) lwz r4,4(r4) Which is exactly the same number of registers used and same length as before. It also simplifies the mess in darwin.md a little further.
I have not bootstrapped this yet. I can do that tomorrow if people this is the correct approach.
Thanks, Andrew Pinski
Attachment:
t.diff.txt
Description: Text document
| Index Nav: | [Date Index] [Subject Index] [Author Index] [Thread Index] | |
|---|---|---|
| Message Nav: | [Date Prev] [Date Next] | [Thread Prev] [Thread Next] |