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Re: target/7282: powerpc64 SImode in FPR
- From: Alan Modra <amodra at bigpond dot net dot au>
- To: nobody at gcc dot gnu dot org
- Cc: gcc-prs at gcc dot gnu dot org,
- Date: 14 Jul 2002 05:46:02 -0000
- Subject: Re: target/7282: powerpc64 SImode in FPR
- Reply-to: Alan Modra <amodra at bigpond dot net dot au>
The following reply was made to PR target/7282; it has been noted by GNATS.
From: Alan Modra <amodra@bigpond.net.au>
To: David Edelsohn <dje@watson.ibm.com>
Cc: gcc-gnats@gcc.gnu.org, gcc-patches@gcc.gnu.org
Subject: Re: target/7282: powerpc64 SImode in FPR
Date: Sun, 14 Jul 2002 15:15:21 +0930
On Sat, Jul 13, 2002 at 10:18:54AM -0400, David Edelsohn wrote:
> This looks okay except for
>
> + [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
> + (float:DF (match_operand:SI 1 "gpc_reg_operand" "*f")))
> + (clobber (match_operand:DI 2 "memory_operand" "=o"))
> + (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
> + (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
>
> The input SImode operand should have constraint "r", not "*f". The whole
> point of this pattern is to move the SImode operand from the GPR to the
> FPR because GCC sometimes gets confused when asked to do this itself.
> SImode is not allowed in FPRs, so the "*f" constraint is contradictory.
Revised patch follows, incorporating your floatunssidf2 suggestion too.
PR target/7282
* config/rs6000/rs6000.md (floatsidf2): Enable for POWERPC64.
(floatunssidf2): Likewise.
(floatsidf_ppc64): New insn_and_split.
(floatunssidf_ppc64): Likewise.
--
Alan Modra
IBM OzLabs - Linux Technology Centre
Index: gcc/config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.192
diff -u -p -r1.192 rs6000.md
--- gcc/config/rs6000/rs6000.md 3 Jul 2002 14:41:22 -0000 1.192
+++ gcc/config/rs6000/rs6000.md 14 Jul 2002 05:38:17 -0000
@@ -5350,9 +5350,18 @@
(clobber (match_dup 4))
(clobber (match_dup 5))
(clobber (match_dup 6))])]
- "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT"
"
{
+ if (TARGET_POWERPC64)
+ {
+ rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
+ rtx t1 = gen_reg_rtx (DImode);
+ rtx t2 = gen_reg_rtx (DImode);
+ emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
+ DONE;
+ }
+
operands[2] = force_reg (SImode, GEN_INT (0x43300000));
operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
@@ -5417,9 +5426,19 @@
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
- "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT"
"
{
+ if (TARGET_POWERPC64)
+ {
+ rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
+ rtx t1 = gen_reg_rtx (DImode);
+ rtx t2 = gen_reg_rtx (DImode);
+ emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
+ t1, t2));
+ DONE;
+ }
+
operands[2] = force_reg (SImode, GEN_INT (0x43300000));
operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
@@ -5533,6 +5552,38 @@
(float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"fcfid %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_insn_and_split "floatsidf_ppc64"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
+ (clobber (match_operand:DI 2 "memory_operand" "=o"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
+ (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ "#"
+ ""
+ [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
+ (set (match_dup 2) (match_dup 3))
+ (set (match_dup 4) (match_dup 2))
+ (set (match_dup 0) (float:DF (match_dup 4)))]
+ ""
+ [(set_attr "type" "fp")])
+
+(define_insn_and_split "floatunssidf_ppc64"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
+ (clobber (match_operand:DI 2 "memory_operand" "=o"))
+ (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
+ (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+ "#"
+ ""
+ [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
+ (set (match_dup 2) (match_dup 3))
+ (set (match_dup 4) (match_dup 2))
+ (set (match_dup 0) (float:DF (match_dup 4)))]
+ ""
[(set_attr "type" "fp")])
(define_insn "fix_truncdfdi2"