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Re: target/7282: powerpc64 SImode in FPR


The following reply was made to PR target/7282; it has been noted by GNATS.

From: Alan Modra <amodra@bigpond.net.au>
To: gcc-gnats@gcc.gnu.org
Cc: gcc-patches@gcc.gnu.org, David Edelsohn <dje@watson.ibm.com>
Subject: Re: target/7282: powerpc64 SImode in FPR
Date: Sat, 13 Jul 2002 21:05:15 +0930

 This cures the ICE.  Thanks to dje for putting me on the right track.
 
 gcc/ChangeLog
 	PR 7282
 	* config/rs6000/rs6000.md (floatsidf2): Enable for POWERPC64.
 	(floatsidf_ppc64): New insn_and_split.
 
 Checked with gcc-3.1 i686-linux -> powerpc64-linux cross-compiler.
 Bootstrapping and regresssion testing powerpc-linux mainline just to
 be sure.
 
 -- 
 Alan Modra
 IBM OzLabs - Linux Technology Centre
 
 diff -up gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.md gcc-ppc64-31/gcc/config/rs6000/rs6000.md
 --- gcc-ppc64-31.orig/gcc/config/rs6000/rs6000.md	2002-07-04 19:40:32.000000000 +0930
 +++ gcc-ppc64-31/gcc/config/rs6000/rs6000.md	2002-07-13 20:26:05.000000000 +0930
 @@ -5271,9 +5428,18 @@
  	      (clobber (match_dup 4))
  	      (clobber (match_dup 5))
  	      (clobber (match_dup 6))])]
 -  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
 +  "TARGET_HARD_FLOAT"
    "
  {
 +  if (TARGET_POWERPC64)
 +    {
 +      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
 +      rtx t1 = gen_reg_rtx (DImode);
 +      rtx t2 = gen_reg_rtx (DImode);
 +      emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
 +      DONE;
 +    }
 +
    operands[2] = force_reg (SImode, GEN_INT (0x43300000));
    operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
    operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
 @@ -5456,6 +5622,22 @@
    "fcfid %0,%1"
    [(set_attr "type" "fp")])
  
 +(define_insn_and_split "floatsidf_ppc64"
 +  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
 +	(float:DF (match_operand:SI 1 "gpc_reg_operand" "*f")))
 +   (clobber (match_operand:DI 2 "memory_operand" "=o"))
 +   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
 +   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
 +  "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
 +  "#"
 +  ""
 +  [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
 +   (set (match_dup 2) (match_dup 3))
 +   (set (match_dup 4) (match_dup 2))
 +   (set (match_dup 0) (float:DF (match_dup 4)))]
 +  ""
 +  [(set_attr "type" "fp")])
 +
  (define_insn "fix_truncdfdi2"
    [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
  	(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]


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