This is the mail archive of the
gcc-prs@gcc.gnu.org
mailing list for the GCC project.
Re: optimization/3712: abort in gen_umulsi3_highpart
- To: nobody at gcc dot gnu dot org
- Subject: Re: optimization/3712: abort in gen_umulsi3_highpart
- From: Richard Henderson <rth at redhat dot com>
- Date: 22 Jul 2001 01:06:00 -0000
- Cc: gcc-prs at gcc dot gnu dot org,
- Reply-To: Richard Henderson <rth at redhat dot com>
The following reply was made to PR optimization/3712; it has been noted by GNATS.
From: Richard Henderson <rth@redhat.com>
To: Andreas Schwab <schwab@suse.de>
Cc: gcc-gnats@gcc.gnu.org, gcc-bugs@gcc.gnu.org
Subject: Re: optimization/3712: abort in gen_umulsi3_highpart
Date: Sat, 21 Jul 2001 17:57:56 -0700
The m68k backend appears to be very confused on this issue.
All constants are sign-extended. Thus it makes no sense to
ask whether an SImode operand is uint32.
It would matter when asking about a DImode operand, but that
is not the case with umulsi3_highpart.
See if this works for you.
r~
* m68k.c (const_uint32_operand): Abort if mode is <= 32 bits.
(const_sint32_operand): Likewise.
* m68k.md (anon mulsi pattern): Use const_int_operand not
const_sint32_operand.
(umulsi3_highpart): Zero extend a constant input.
(smulsi3_highpart): Don't bother checking SImode constant.
(const_umulsi3_highpart): Give op3 DImode.
(const_smulsi3_highpart): Likewise.
Index: m68k.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/m68k/m68k.c,v
retrieving revision 1.48
diff -c -p -d -r1.48 m68k.c
*** m68k.c 2001/07/17 06:54:45 1.48
--- m68k.c 2001/07/22 00:52:14
*************** strict_low_part_peephole_ok (mode, first
*** 3937,3944 ****
int
const_uint32_operand (op, mode)
rtx op;
! enum machine_mode mode ATTRIBUTE_UNUSED;
{
#if HOST_BITS_PER_WIDE_INT > 32
/* All allowed constants will fit a CONST_INT. */
return (GET_CODE (op) == CONST_INT
--- 3937,3949 ----
int
const_uint32_operand (op, mode)
rtx op;
! enum machine_mode mode;
{
+ /* It doesn't make sense to ask this question with a mode that is
+ not larger than 32 bits. */
+ if (GET_MODE_BITSIZE (mode) <= 32)
+ abort ();
+
#if HOST_BITS_PER_WIDE_INT > 32
/* All allowed constants will fit a CONST_INT. */
return (GET_CODE (op) == CONST_INT
*************** const_uint32_operand (op, mode)
*** 3956,3963 ****
int
const_sint32_operand (op, mode)
rtx op;
! enum machine_mode mode ATTRIBUTE_UNUSED;
{
/* All allowed constants will fit a CONST_INT. */
return (GET_CODE (op) == CONST_INT
&& (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
--- 3961,3973 ----
int
const_sint32_operand (op, mode)
rtx op;
! enum machine_mode mode;
{
+ /* It doesn't make sense to ask this question with a mode that is
+ not larger than 32 bits. */
+ if (GET_MODE_BITSIZE (mode) <= 32)
+ abort ();
+
/* All allowed constants will fit a CONST_INT. */
return (GET_CODE (op) == CONST_INT
&& (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
Index: m68k.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/m68k/m68k.md,v
retrieving revision 1.42
diff -c -p -d -r1.42 m68k.md
*** m68k.md 2001/07/20 20:19:12 1.42
--- m68k.md 2001/07/22 00:52:14
***************
*** 3146,3152 ****
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
! (match_operand:SI 2 "const_sint32_operand" "")))
(set (match_operand:SI 3 "register_operand" "=d")
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(match_dup 2))
--- 3146,3152 ----
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
! (match_operand:SI 2 "const_int_operand" "n")))
(set (match_operand:SI 3 "register_operand" "=d")
(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
(match_dup 2))
***************
*** 3167,3177 ****
"
{
operands[3] = gen_reg_rtx (SImode);
! if (GET_CODE (operands[2]) == CONST_INT
! || GET_CODE (operands[2]) == CONST_DOUBLE)
{
! if (! const_uint32_operand (operands[2], VOIDmode))
! abort ();
/* We have to adjust the operand order for the matching constraints. */
emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
operands[1], operands[2]));
--- 3167,3178 ----
"
{
operands[3] = gen_reg_rtx (SImode);
!
! if (GET_CODE (operands[2]) == CONST_INT)
{
! operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
! 0, DImode);
!
/* We have to adjust the operand order for the matching constraints. */
emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
operands[1], operands[2]));
***************
*** 3195,3201 ****
(truncate:SI
(lshiftrt:DI
(mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
! (match_operand 3 "const_uint32_operand" ""))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020 && !TARGET_68060 && !TARGET_5200"
--- 3196,3202 ----
(truncate:SI
(lshiftrt:DI
(mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
! (match_operand:DI 3 "const_uint32_operand" "n"))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020 && !TARGET_68060 && !TARGET_5200"
***************
*** 3214,3224 ****
"
{
operands[3] = gen_reg_rtx (SImode);
! if (GET_CODE (operands[2]) == CONST_INT
! || GET_CODE (operands[2]) == CONST_DOUBLE)
{
- if (! const_sint32_operand (operands[2], VOIDmode))
- abort ();
/* We have to adjust the operand order for the matching constraints. */
emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
operands[1], operands[2]));
--- 3215,3222 ----
"
{
operands[3] = gen_reg_rtx (SImode);
! if (GET_CODE (operands[2]) == CONST_INT)
{
/* We have to adjust the operand order for the matching constraints. */
emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
operands[1], operands[2]));
***************
*** 3242,3248 ****
(truncate:SI
(lshiftrt:DI
(mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
! (match_operand 3 "const_sint32_operand" ""))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020 && !TARGET_68060 && !TARGET_5200"
--- 3240,3246 ----
(truncate:SI
(lshiftrt:DI
(mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
! (match_operand:DI 3 "const_sint32_operand" "n"))
(const_int 32))))
(clobber (match_operand:SI 1 "register_operand" "=d"))]
"TARGET_68020 && !TARGET_68060 && !TARGET_5200"