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Re: [PATCH] Support multiple registers for the frame pointer
- From: Richard Sandiford <richard dot sandiford at arm dot com>
- To: Dimitar Dimitrov <dimitar at dinux dot eu>
- Cc: gcc-patches at gcc dot gnu dot org, Kwok Cheung Yeung <kcy at codesourcery dot com>
- Date: Tue, 05 Nov 2019 17:14:59 +0000
- Subject: Re: [PATCH] Support multiple registers for the frame pointer
- References: <3a1551a1-b44e-29c6-841f-24d8a54a002c@codesourcery.com> <7924754.r1buTDnsWX@tpdeb>
Dimitar Dimitrov <dimitar@dinux.eu> writes:
> On Sat, 2 Nov 2019, 19:28:38 EET Kwok Cheung Yeung wrote:
>> The AMD GCN architecture uses 64-bit pointers, but the scalar registers
>> are 32-bit wide, so pointers must reside in a pair of registers.
> ...
>> Bootstrapped on x86_64 and tested with no regressions, which is not
>> surprising as nothing different happens when the FP fits into a single
>> register. I believe this is true for the 64-bit variants of the more
>> popular architectures as well (ARM, RS6000, MIPS, Sparc). Are there any
>> other architectures similar to GCN (i.e. 64-bit pointers with 32-bit GPRs)?
> Yes. PRU uses four 8-bit HW registers to hold 32-bit pointers.
>
>>
> ...
>> diff --git a/gcc/ira.c b/gcc/ira.c
>> index 9f8da67..25e9359 100644
>> --- a/gcc/ira.c
>> +++ b/gcc/ira.c
>> @@ -515,7 +515,13 @@ setup_alloc_regs (bool use_hard_frame_p)
>> #endif
>> no_unit_alloc_regs = fixed_nonglobal_reg_set;
>> if (! use_hard_frame_p)
>> - SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM);
>> + {
>> + int fp_reg_count = hard_regno_nregs (HARD_FRAME_POINTER_REGNUM,
>> Pmode);
>> + for (int reg = HARD_FRAME_POINTER_REGNUM;
>> + reg < HARD_FRAME_POINTER_REGNUM + fp_reg_count;
>> + reg++)
>> + SET_HARD_REG_BIT (no_unit_alloc_regs, reg);
>> + }
> Please consider using the existing helper function instead:
> add_to_hard_reg_set (&no_unit_alloc_regs, Pmode, reg);
+1