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Re: [PATCH 1/2] gcc/riscv: Include more registers in SIBCALL_REGS
On Thu, Aug 22, 2019 at 10:30 PM Jim Wilson <jimw@sifive.com> wrote:
>
> On Mon, Aug 19, 2019 at 12:15 PM Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > I don't see any reason why we couldn't add t1, and a0 to a7 into this
> > set, and this is what this patch does.
>
> SIBCALL_REGS already includes t1 and t2. It is t0 aka x5 that is
> missing. I think this is wrong. As Andrew mentioned, this will
> penalize any target that has a call-stack aware branch predictor. We
> could add a tune flag for that, but it doesn't seem worth the effort.
> Adding the other regs a0 to a7 is OK. They won't be used unless they
> are available. This is OK without the t0/x5 change.
While reviewing the second part of the patch set, I noticed that I
missed riscv_regno_to_class. A change to SIBCALL_REGS requires a
corresponding change to riscv_regno_class. SIBCALL_REGS is the
smallest class, so you just need to change the entries for a0 to a7
from JALR_REGS to SIBCALL_REGS.
Jim