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Re: [AArch64] Add a "y" constraint for V0-V7
- From: Richard Sandiford <richard dot sandiford at arm dot com>
- To: James Greenhalgh <james dot greenhalgh at arm dot com>
- Cc: gcc-patches at gcc dot gnu dot org, richard dot earnshaw at arm dot com, marcus dot shawcroft at arm dot com, nd at arm dot com
- Date: Tue, 13 Aug 2019 10:48:42 +0100
- Subject: Re: [AArch64] Add a "y" constraint for V0-V7
- References: <email@example.com> <20190812170329.GC8207@arm.com>
James Greenhalgh <firstname.lastname@example.org> writes:
> On Wed, Aug 07, 2019 at 07:19:12PM +0100, Richard Sandiford wrote:
>> Some indexed SVE FCMLA operations have a 3-bit register field that
>> requires one of Z0-Z7. This patch adds a public "y" constraint for that.
>> The patch also documents "x", which is again intended to be a public
>> Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf.
>> OK to install?
> I had the vague recollection that 'y' already meant something... I'm
> guessing you already checked, but just in case, please check.
Yeah, it's definitely unused at the moment. It might be this usage that
you're remembering, since we unofficially "reserved" "y" for it a few
years back. (It was a nice coincidence that the w/x/y sequence was still
free to mean 32/16/8 FP registers. :-))
> Otherwise, this is OK.
>> 2019-08-07 Richard Sandiford <email@example.com>
>> * doc/md.texi: Document the x and y constraints for AArch64.
>> * config/aarch64/aarch64.h (FP_LO8_REGNUM_P): New macro.
>> (FP_LO8_REGS): New reg_class.
>> (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add an entry for FP_LO8_REGS.
>> * config/aarch64/aarch64.c (aarch64_hard_regno_nregs)
>> (aarch64_regno_regclass, aarch64_class_max_nregs): Handle FP_LO8_REGS.
>> * config/aarch64/predicates.md (aarch64_simd_register): Use
>> FP_REGNUM_P instead of checking the classes manually.
>> * config/aarch64/constraints.md (y): New constraint.
>> * gcc.target/aarch64/asm-x-constraint-1.c: New test.
>> * gcc.target/aarch64/asm-y-constraint-1.c: Likewise.