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[AArch64] Remove redundant SVE FADDA pattern


*pred_fold_left_plus_<mode> could no longer match anything, since
UNSPEC_FADDA now takes three operands.  Predicated FADDAs should
now go through mask_fold_left_plus_<mode> instead.

Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf.
Applied as r274186.

Richard


2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (*pred_fold_left_plus_<mode>): Delete.

Index: gcc/config/aarch64/aarch64-sve.md
===================================================================
--- gcc/config/aarch64/aarch64-sve.md	2019-08-07 19:37:15.646555313 +0100
+++ gcc/config/aarch64/aarch64-sve.md	2019-08-07 19:45:18.526961399 +0100
@@ -3468,21 +3468,6 @@ (define_insn "mask_fold_left_plus_<mode>
   "fadda\t%<Vetype>0, %3, %<Vetype>0, %2.<Vetype>"
 )
 
-;; Predicated form of the above in-order reduction.
-(define_insn "*pred_fold_left_plus_<mode>"
-  [(set (match_operand:<VEL> 0 "register_operand" "=w")
-	(unspec:<VEL>
-	  [(match_operand:<VEL> 1 "register_operand" "0")
-	   (unspec:SVE_F
-	     [(match_operand:<VPRED> 2 "register_operand" "Upl")
-	      (match_operand:SVE_F 3 "register_operand" "w")
-	      (match_operand:SVE_F 4 "aarch64_simd_imm_zero")]
-	     UNSPEC_SEL)]
-	  UNSPEC_FADDA))]
-  "TARGET_SVE"
-  "fadda\t%<Vetype>0, %2, %<Vetype>0, %3.<Vetype>"
-)
-
 ;; =========================================================================
 ;; == Permutes
 ;; =========================================================================


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