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[PATCH v2 11/18] Use REG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh REG
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md: Convert GET_CODE (..) == REG
to REG_P (..).
* config/aarch64/predicates.md: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/arc.md: Likewise.
* config/arc/predicates.md: Likewise.
* config/arm/arm.c: Likewise.
* config/bfin/bfin.c: Likewise.
* config/bfin/bfin.md: Likewise.
* config/c6x/c6x.c: Likewise.
* config/c6x/c6x.md: Likewise.
* config/c6x/predicates.md: Likewise.
* config/cr16/cr16.c: Likewise.
* config/cr16/cr16.h: Likewise.
* config/csky/csky.c: Likewise.
* config/csky/csky.md: Likewise.
* config/csky/predicates.md: Likewise.
* config/darwin.c: Likewise.
* config/epiphany/epiphany.c: Likewise.
* config/epiphany/predicates.md: Likewise.
* config/fr30/fr30.c: Likewise.
* config/fr30/fr30.h: Likewise.
* config/fr30/fr30.md: Likewise.
* config/fr30/predicates.md: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/frv.md: Likewise.
* config/frv/predicates.md: Likewise.
* config/ft32/constraints.md: Likewise.
* config/ft32/ft32.c: Likewise.
* config/ft32/ft32.md: Likewise.
* config/ft32/predicates.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/h8300/h8300.c: Likewise.
* config/h8300/h8300.md: Likewise.
* config/h8300/predicates.md: Likewise.
* config/i386/i386-expand.c: Likewise.
* config/i386/i386-features.c: Likewise.
* config/i386/predicates.md: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/ia64.md: Likewise.
* config/ia64/predicates.md: Likewise.
* config/iq2000/iq2000.c: Likewise.
* config/iq2000/iq2000.md: Likewise.
* config/iq2000/predicates.md: Likewise.
* config/lm32/lm32.c: Likewise.
* config/lm32/lm32.md: Likewise.
* config/m32c/m32c.c: Likewise.
* config/m32c/predicates.md: Likewise.
* config/m68k/m68k.c: Likewise.
* config/m68k/m68k.md: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mcore/mcore.md: Likewise.
* config/mcore/predicates.md: Likewise.
* config/microblaze/constraints.md: Likewise.
* config/microblaze/microblaze.c: Likewise.
* config/microblaze/microblaze.h: Likewise.
* config/microblaze/microblaze.md: Likewise.
* config/microblaze/predicates.md: Likewise.
* config/mips/mips.c: Likewise.
* config/mn10300/predicates.md: Likewise.
* config/moxie/moxie.md: Likewise.
* config/moxie/predicates.md: Likewise.
* config/msp430/msp430.c: Likewise.
* config/nds32/nds32-fp-as-gp.c: Likewise.
* config/nds32/nds32-md-auxiliary.c: Likewise.
* config/nds32/nds32-multiple.md: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nds32/nds32-relax-opt.c: Likewise.
* config/nds32/nds32.c: Likewise.
* config/nios2/predicates.md: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.md: Likewise.
* config/pdp11/pdp11.c: Likewise.
* config/pdp11/pdp11.md: Likewise.
* config/pru/predicates.md: Likewise.
* config/pru/pru.c: Likewise.
* config/pru/pru.md: Likewise.
* config/riscv/constraints.md: Likewise.
* config/rl78/rl78.c: Likewise.
* config/rx/rx.c: Likewise.
* config/rx/rx.md: Likewise.
* config/s390/predicates.md: Likewise.
* config/s390/s390.c: Likewise.
* config/s390/s390.md: Likewise.
* config/sparc/sparc.c: Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/constraints.md: Likewise.
* config/spu/spu.c: Likewise.
* config/spu/spu.md: Likewise.
* config/v850/predicates.md: Likewise.
* config/v850/v850.c: Likewise.
* config/v850/v850.md: Likewise.
* config/visium/predicates.md: Likewise.
* config/visium/visium.c: Likewise.
* config/visium/visium.md: Likewise.
* config/xtensa/predicates.md: Likewise.
* config/xtensa/xtensa.c: Likewise.
* config/xtensa/xtensa.md: Likewise.
* cse.c: Likewise.
* dse.c: Likewise.
* ira-costs.c: Likewise.
* ira.c: Likewise.
* lra-constraints.c: Likewise.
* mode-switching.c: Likewise.
* read-rtl-function.c: Likewise.
* ree.c: Likewise.
* regrename.c: Likewise.
* valtrack.c: Likewise.
* var-tracking.c: Likewise.
108 files changed, 798 insertions(+), 798 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index c6ccc99a2aa..0fe7ef60d33 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5257,7 +5257,7 @@
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]);
}
})
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 9f2e139899f..ef01faed19c 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -471,14 +471,14 @@
(and (match_operand 0 "general_operand")
(match_test "!MEM_P (op)
|| GET_CODE (XEXP (op, 0)) == POST_INC
- || GET_CODE (XEXP (op, 0)) == REG")))
+ || REG_P (XEXP (op, 0))")))
;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
(define_predicate "aarch64_simd_nonimmediate_operand"
(and (match_operand 0 "nonimmediate_operand")
(match_test "!MEM_P (op)
|| GET_CODE (XEXP (op, 0)) == POST_INC
- || GET_CODE (XEXP (op, 0)) == REG")))
+ || REG_P (XEXP (op, 0))")))
;; Predicates used by the various SIMD shift operations. These
;; fall in to 3 categories.
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index d9225440c3f..e417756a9f4 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -830,7 +830,7 @@ arc_sched_adjust_priority (rtx_insn *insn, int priority)
rtx set = single_set (insn);
if (set
&& GET_MODE (SET_SRC(set)) == DFmode
- && GET_CODE (SET_SRC(set)) == REG)
+ && REG_P (SET_SRC(set)))
{
/* Incrementing priority by 20 (empirically derived). */
return priority + 20;
@@ -2483,7 +2483,7 @@ arc_address_cost (rtx addr, machine_mode, addr_space_t, bool speed)
register rtx plus0 = XEXP (addr, 0);
register rtx plus1 = XEXP (addr, 1);
- if (GET_CODE (plus0) != REG
+ if (!REG_P (plus0)
&& (GET_CODE (plus0) != MULT
|| !CONST_INT_P (XEXP (plus0, 1))
|| (INTVAL (XEXP (plus0, 1)) != 2
@@ -4593,7 +4593,7 @@ arc_print_operand (FILE *file, rtx x, int code)
case 'R' :
/* Write second word of DImode or DFmode reference,
register or memory. */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names[REGNO (x)+1], file);
else if (GET_CODE (x) == MEM)
{
@@ -4683,7 +4683,7 @@ arc_print_operand (FILE *file, rtx x, int code)
break;
case 'H' :
case 'L' :
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
/* L = least significant word, H = most significant word. */
if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
@@ -10953,17 +10953,17 @@ compact_memory_operand_p (rtx op, machine_mode mode,
plus0 = XEXP (addr, 0);
plus1 = XEXP (addr, 1);
- if ((GET_CODE (plus0) == REG)
+ if ((REG_P (plus0))
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (plus0)))
- && ((GET_CODE (plus1) == REG)
+ && ((REG_P (plus1))
&& ((REGNO (plus1) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (plus1)))))
{
return !av2short;
}
- if ((GET_CODE (plus0) == REG)
+ if ((REG_P (plus0))
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| (COMPACT_GP_REG_P (REGNO (plus0)) && !av2short)
|| (IN_RANGE (REGNO (plus0), 0, 31) && av2short))
@@ -11033,10 +11033,10 @@ compact_memory_operand_p (rtx op, machine_mode mode,
}
if ((GET_CODE (plus0) == MULT)
- && (GET_CODE (XEXP (plus0, 0)) == REG)
+ && (REG_P (XEXP (plus0, 0)))
&& ((REGNO (XEXP (plus0, 0)) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (XEXP (plus0, 0))))
- && (GET_CODE (plus1) == REG)
+ && (REG_P (plus1))
&& ((REGNO (plus1) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (plus1))))
return scaled;
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 63b65d533a4..96d6ffbcb11 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4163,7 +4163,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
32 bit address of the callee into a register before performing the
branch and link - this exposes cse opportunities.
Also, in weird cases like compile/20010107-1.c, we may get a PLUS. */
- if (GET_CODE (callee) != REG
+ if (!REG_P (callee)
&& (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee)))
XEXP (operands[0], 0) = force_reg (Pmode, callee);
}
@@ -4209,7 +4209,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
gcc_assert (MEM_P (operands[1]));
callee = XEXP (operands[1], 0);
/* See the comment in define_expand \"call\". */
- if (GET_CODE (callee) != REG
+ if (!REG_P (callee)
&& (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee)))
XEXP (operands[1], 0) = force_reg (Pmode, callee);
}")
@@ -4711,7 +4711,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
if (operands[2] == NULL_RTX)
operands[2] = const0_rtx;
- if (GET_CODE (callee) != REG
+ if (!REG_P (callee)
&& (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee)))
XEXP (operands[0], 0) = force_reg (Pmode, callee);
}"
@@ -4730,7 +4730,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
if (operands[3] == NULL_RTX)
operands[3] = const0_rtx;
- if (GET_CODE (callee) != REG && arc_is_longcall_p (callee))
+ if (!REG_P (callee) && arc_is_longcall_p (callee))
XEXP (operands[1], 0) = force_reg (Pmode, callee);
}"
)
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index 0c2926dc5e1..01bfc1b9547 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -162,7 +162,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG)
+ return (REG_P (op))
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| COMPACT_GP_REG_P (REGNO (op))) ;
}
@@ -174,7 +174,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG)
+ return (REG_P (op))
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| (TARGET_V2 && REGNO (op) <= 31 && REGNO (op) != 30)
|| !TARGET_V2);
@@ -219,7 +219,7 @@
plus0 = XEXP (addr, 0);
plus1 = XEXP (addr, 1);
- if ((GET_CODE (plus0) == REG)
+ if ((REG_P (plus0))
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (plus0)))
&& (CONST_INT_P (plus1)))
@@ -241,7 +241,7 @@
}
}
- if ((GET_CODE (plus0) == REG)
+ if ((REG_P (plus0))
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| SP_REG_P (REGNO (plus0)))
&& (CONST_INT_P (plus1)))
@@ -483,7 +483,7 @@
return FALSE;
}
- if (mode == GET_MODE (op) && GET_CODE (op) == REG && REGNO (op) == CC_REG)
+ if (mode == GET_MODE (op) && REG_P (op) && REGNO (op) == CC_REG)
return TRUE;
return FALSE;
@@ -622,7 +622,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == DOUBLE_REGS));
})
@@ -640,7 +640,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS));
})
@@ -654,10 +654,10 @@
if ((GET_CODE (op) == MEM)
&& (mode == V8HImode)
- && GET_CODE (XEXP (op,0)) == REG)
+ && REG_P (XEXP (op,0)))
return 1;
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS));
})
@@ -672,7 +672,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == SIMD_DMA_CONFIG_REGS));
})
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a6b493f2973..c67b7c97dcc 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -31168,7 +31168,7 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset)
if (GET_CODE (addr) == CONST)
addr = XEXP (addr, 0);
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
{
*base = addr;
*offset = const0_rtx;
@@ -31176,7 +31176,7 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset)
}
if (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& CONST_INT_P (XEXP (addr, 1)))
{
*base = XEXP (addr, 0);
@@ -31207,12 +31207,12 @@ fusion_load_store (rtx_insn *insn, rtx *base, rtx *offset, bool *is_load)
src = SET_SRC (x);
dest = SET_DEST (x);
- if (GET_CODE (src) == REG && GET_CODE (dest) == MEM)
+ if (REG_P (src) && GET_CODE (dest) == MEM)
{
*is_load = false;
extract_base_offset_in_addr (dest, base, offset);
}
- else if (GET_CODE (src) == MEM && GET_CODE (dest) == REG)
+ else if (GET_CODE (src) == MEM && REG_P (dest))
{
*is_load = true;
extract_base_offset_in_addr (src, base, offset);
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index dea2ee7cde5..7f8424b5f5d 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -1224,7 +1224,7 @@ bfin_delegitimize_address (rtx orig_x)
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 1)) == UNSPEC
&& XINT (XEXP (x, 1), 1) == UNSPEC_MOVE_PIC
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
return XVECEXP (XEXP (x, 1), 0, 0);
@@ -1958,7 +1958,7 @@ expand_move (rtx *operands, machine_mode mode)
register */
else if ((reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) == MEM
- && GET_CODE (operands[1]) != REG)
+ && !REG_P (operands[1]))
operands[1] = force_reg (mode, operands[1]);
return false;
}
@@ -2874,8 +2874,8 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
}
}
*total = cost2;
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += set_src_cost (op0, mode, speed);
#if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
towards creating too many induction variables. */
@@ -2889,8 +2889,8 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
if (!CONST_INT_P (op1)
|| !satisfies_constraint_Ks7 (op1))
*total += rtx_cost (op1, mode, PLUS, 1, speed);
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, PLUS, 0, speed);
}
return true;
@@ -2912,8 +2912,8 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, code, 0, speed);
return true;
@@ -2937,8 +2937,8 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
}
}
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, code, 0, speed);
if (mode == DImode)
@@ -2996,11 +2996,11 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
else
*total = COSTS_N_INSNS (3);
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, MULT, 0, speed);
- if (GET_CODE (op1) != REG
- && (GET_CODE (op1) != SUBREG || GET_CODE (SUBREG_REG (op1)) != REG))
+ if (!REG_P (op1)
+ && (GET_CODE (op1) != SUBREG || !REG_P (SUBREG_REG (op1))))
*total += rtx_cost (op1, mode, MULT, 1, speed);
}
return true;
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 517ee4baa39..2c70db8b39b 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -505,7 +505,7 @@
(define_insn_and_split "movdi_insn"
[(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
(match_operand:DI 1 "general_operand" "iFx,r,mx"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"#"
"reload_completed"
[(set (match_dup 2) (match_dup 3))
@@ -607,7 +607,7 @@
(define_insn "*movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr")
(match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
%0 = %1;
%0 = %1;
@@ -647,7 +647,7 @@
[(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
(match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
#
%0 = %1;
@@ -669,7 +669,7 @@
(define_insn "*movhi_insn"
[(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
(match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
{
static const char *templates[] = {
"%0 = %1;",
@@ -693,7 +693,7 @@
(define_insn "*movqi_insn"
[(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
(match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
%0 = %1;
%0 = %1 (X);
@@ -706,7 +706,7 @@
(define_insn "*movsf_insn"
[(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
(match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
%0 = %1;
#
@@ -717,7 +717,7 @@
(define_insn_and_split "movdf_insn"
[(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
(match_operand:DF 1 "general_operand" "iFx,r,mx"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"#"
"reload_completed"
[(set (match_dup 2) (match_dup 3))
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index 62fab8376be..fe78ed0dfce 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -1375,7 +1375,7 @@ expand_move (rtx *operands, machine_mode mode)
rtx op = operands[1];
if ((reload_in_progress | reload_completed) == 0
- && GET_CODE (dest) == MEM && GET_CODE (op) != REG)
+ && GET_CODE (dest) == MEM && !REG_P (op))
operands[1] = force_reg (mode, op);
else if (mode == SImode && symbolic_operand (op, SImode))
{
@@ -2219,7 +2219,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
case 'p':
case 'P':
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
v = REGNO (x);
if (code == 'P')
v++;
@@ -6174,11 +6174,11 @@ c6x_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, int *total,
else if (mode == HImode)
*total = COSTS_N_INSNS (speed ? 2 : 1);
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, MULT, 0, speed);
- if (op1 && GET_CODE (op1) != REG
- && (GET_CODE (op1) != SUBREG || GET_CODE (SUBREG_REG (op1)) != REG))
+ if (op1 && !REG_P (op1)
+ && (GET_CODE (op1) != SUBREG || !REG_P (SUBREG_REG (op1))))
*total += rtx_cost (op1, mode, MULT, 1, speed);
return true;
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index 3707e80697c..2b35d6717cb 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -602,7 +602,7 @@
"=a,b, a, b, ab, ab,a,?a, b,?b, Q, R, R, Q")
(match_operand:QIHIM 1 "general_operand"
"a,b,?b,?a,Is5,IsB,Q, R, R, Q, a,?a, b,?b"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
%|%.\\tmv\\t%$\\t%1, %0
%|%.\\tmv\\t%$\\t%1, %0
@@ -631,7 +631,7 @@
"=a,b, a, b, ab, ab,a,b,ab,a,?a, b,?b, Q, R, R, Q")
(match_operand:SISFVM 1 "general_operand"
"a,b,?b,?a,Is5,IsB,S0,S0,Si,Q, R, R, Q, a,?a, b,?b"))]
- "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG
+ "(GET_CODE (operands[0]) != MEM || REG_P (operands[1])
|| (GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))))"
"@
%|%.\\tmv\\t%$\\t%1, %0
diff --git a/gcc/config/c6x/predicates.md b/gcc/config/c6x/predicates.md
index ea360f95543..b933de8b9dc 100644
--- a/gcc/config/c6x/predicates.md
+++ b/gcc/config/c6x/predicates.md
@@ -69,7 +69,7 @@
(define_predicate "c6x_call_operand"
(ior (match_code "symbol_ref,reg")
(and (match_code "subreg")
- (match_test "GET_CODE (XEXP (op, 0)) == REG")))
+ (match_test "REG_P (XEXP (op, 0))")))
{
/* The linker transforms jumps to undefined weak symbols in a way that
is incompatible with our code generation. */
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 9c9c4779eb2..4cdb58b06bb 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -1483,7 +1483,7 @@ cr16_print_operand (FILE * file, rtx x, int code)
return;
case 'p':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
/* For Push instructions, we should not print register pairs. */
fprintf (file, "%s", reg_names[REGNO (x)]);
diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h
index 91e96ba67b3..227b536d1c9 100644
--- a/gcc/config/cr16/cr16.h
+++ b/gcc/config/cr16/cr16.h
@@ -341,9 +341,9 @@ enum reg_class
/* This check is for sbit/cbit instruction. */
#define OK_FOR_Z(OP) \
((GET_CODE (OP) == MEM && CONST_INT_P (XEXP (OP, 0))) \
- || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \
+ || (GET_CODE (OP) == MEM && REG_P (XEXP (OP, 0))) \
|| (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
- && GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \
+ && REG_P (XEXP ((XEXP (OP, 0)), 0)) \
&& CONST_INT_P (XEXP ((XEXP (OP, 0)), 1))))
/* Stack layout and calling conventions. */
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 85850c8be1f..6d2192a5096 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -2321,11 +2321,11 @@ csky_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
x = SUBREG_REG (x);
}
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
regno = REGNO (x) + off;
}
}
- else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ else if (REG_P (x) || GET_CODE (x) == SUBREG)
regno = true_regnum (x);
/* We always require a general register when copying anything to
@@ -4260,13 +4260,13 @@ csky_output_movedouble (rtx operands[],
&& GET_CODE (XEXP (memexp, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (memexp, 0), 0)) == LABEL_REF))
return "lrw\t%0, [%1]\n\tlrw\t%R0, [%R1]";
- else if (GET_CODE (memexp) == REG)
+ else if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -4318,7 +4318,7 @@ csky_output_movedouble (rtx operands[],
else
gcc_unreachable ();
}
- else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
+ else if (GET_CODE (dst) == MEM && REG_P (src))
{
rtx memexp = XEXP (dst, 0);
int srcreg = REGNO (src);
@@ -4327,13 +4327,13 @@ csky_output_movedouble (rtx operands[],
decompose_csky_address (XEXP (dst, 0), &op0);
- if (GET_CODE (memexp) == REG)
+ if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -4395,13 +4395,13 @@ csky_output_ck801_movedouble (rtx operands[],
&& GET_CODE (XEXP (memexp, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (memexp, 0), 0)) == LABEL_REF))
return "lrw\t%0, [%1]\n\tlrw\t%R0, [%R1]";
- else if (GET_CODE (memexp) == REG)
+ else if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -4440,7 +4440,7 @@ csky_output_ck801_movedouble (rtx operands[],
else
gcc_unreachable ();
}
- else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
+ else if (GET_CODE (dst) == MEM && REG_P (src))
{
rtx memexp = XEXP (dst, 0);
int srcreg = REGNO (src);
@@ -4449,13 +4449,13 @@ csky_output_ck801_movedouble (rtx operands[],
decompose_csky_address (XEXP (dst, 0), &op0);
- if (GET_CODE (memexp) == REG)
+ if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -6530,7 +6530,7 @@ csky_sched_adjust_cost (rtx_insn *insn,
if (REG_P (base))
reg = base;
if (GET_CODE (base) == PLUS
- && GET_CODE (XEXP (base, 0)) == REG)
+ && REG_P (XEXP (base, 0)))
reg = XEXP (base, 0);
if ((reg != NULL_RTX) && reg_set_p (reg, PATTERN (dep)))
return 2;
@@ -6561,7 +6561,7 @@ csky_sched_adjust_cost (rtx_insn *insn,
if (REG_P (base))
reg = base;
if (GET_CODE (base) == PLUS
- && GET_CODE (XEXP (base, 0)) == REG)
+ && REG_P (XEXP (base, 0)))
reg = XEXP (base, 0);
if ((reg != NULL_RTX) && reg_set_p (reg, PATTERN (dep))
&& get_attr_type (dep) != TYPE_LOAD)
diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md
index 7a8b382c1d8..2dd1452eb3b 100644
--- a/gcc/config/csky/csky.md
+++ b/gcc/config/csky/csky.md
@@ -909,7 +909,7 @@
(clobber (reg:CC CSKY_CC_REGNUM))])]
""
"
- if (CSKY_ISA_FEATURE (E1) && (GET_CODE (operands[2]) != REG))
+ if (CSKY_ISA_FEATURE (E1) && (!REG_P (operands[2])))
operands[2] = force_reg (DImode, operands[2]);
"
)
@@ -2060,7 +2060,7 @@
|| GET_CODE (operands[1]) != MEM
|| !REG_P (XEXP (operands[1], 0))
|| XEXP (operands[1], 0) != stack_pointer_rtx
- || GET_CODE (operands[0]) != REG
+ || !REG_P (operands[0])
|| (REGNO (XEXP (operands[1], 0)) > REGNO (operands[0])
&& (REGNO (XEXP (operands[1], 0))
< REGNO (operands[0]) + INTVAL (operands[2]))))
@@ -2098,7 +2098,7 @@
|| GET_CODE (operands[0]) != MEM
|| !REG_P (XEXP (operands[0], 0))
|| XEXP (operands[0], 0) != stack_pointer_rtx
- || GET_CODE (operands[1]) != REG
+ || !REG_P (operands[1])
|| (REGNO (XEXP (operands[0], 0)) >= REGNO (operands[1])
&& (REGNO (XEXP (operands[0], 0))
< REGNO (operands[1]) + INTVAL (operands[2]))))
diff --git a/gcc/config/csky/predicates.md b/gcc/config/csky/predicates.md
index 0c67e4e9cbf..93725f15209 100644
--- a/gcc/config/csky/predicates.md
+++ b/gcc/config/csky/predicates.md
@@ -31,9 +31,9 @@
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+ || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)) != REG
+ || !REG_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0))
|| XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0) != stack_pointer_rtx)
return 0;
@@ -45,7 +45,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != SImode
|| REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
|| GET_CODE (SET_SRC (elt)) != MEM
@@ -73,9 +73,9 @@
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0)) != REG
+ || !REG_P (XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0))
|| XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0) != stack_pointer_rtx
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+ || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return 0;
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -86,7 +86,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
+ || !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != SImode
|| REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
|| GET_CODE (SET_DEST (elt)) != MEM
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 8ccbad46310..9089c4673dc 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -743,7 +743,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
compiler's ignorance on how to move the PIC base register to
other registers. (The reload phase sometimes introduces such
insns.) */
- if (GET_CODE (XEXP (orig, 0)) == REG
+ if (REG_P (XEXP (orig, 0))
&& REGNO (XEXP (orig, 0)) == PIC_OFFSET_TABLE_REGNUM
/* Prevent the same register from being erroneously used
as both the base and index registers. */
@@ -829,7 +829,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
orig = machopic_indirect_data_reference (orig, reg);
if (GET_CODE (orig) == PLUS
- && GET_CODE (XEXP (orig, 0)) == REG)
+ && REG_P (XEXP (orig, 0)))
{
if (reg == 0)
return force_reg (mode, orig);
@@ -917,7 +917,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
#endif /* HAVE_lo_sum */
{
rtx pic = pic_offset_table_rtx;
- if (GET_CODE (pic) != REG)
+ if (!REG_P (pic))
{
emit_move_insn (reg, pic);
pic = reg;
@@ -988,7 +988,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
else
{
rtx pic = pic_offset_table_rtx;
- if (GET_CODE (pic) != REG)
+ if (!REG_P (pic))
{
emit_move_insn (reg, pic);
pic = reg;
@@ -1005,7 +1005,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
}
}
- if (GET_CODE (pic_ref) != REG)
+ if (!REG_P (pic_ref))
{
if (reg != 0)
{
@@ -1027,7 +1027,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
|| GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (orig, 0)) == LABEL_REF)
&& XEXP (orig, 0) != pic_offset_table_rtx
- && GET_CODE (XEXP (orig, 1)) != REG)
+ && !REG_P (XEXP (orig, 1)))
{
rtx base;
diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c
index 11f188f13e0..ea1c137a881 100644
--- a/gcc/config/epiphany/epiphany.c
+++ b/gcc/config/epiphany/epiphany.c
@@ -1417,7 +1417,7 @@ epiphany_print_operand_address (FILE *file, machine_mode /*mode*/, rtx addr)
offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
else
base = XEXP (addr, 0), index = XEXP (addr, 1);
- gcc_assert (GET_CODE (base) == REG);
+ gcc_assert (REG_P (base));
fputs (reg_names[REGNO (base)], file);
if (index == 0)
{
@@ -2674,7 +2674,7 @@ epiphany_expand_set_fp_mode (rtx *operands)
emit_insn (gen_gid ());
emit_move_insn (scratch, ctrl);
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* FP_MODE_CALLER */
emit_insn (gen_xorsi3 (scratch, scratch, src));
diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md
index dc039ffbf6f..6804a75a290 100644
--- a/gcc/config/epiphany/predicates.md
+++ b/gcc/config/epiphany/predicates.md
@@ -96,7 +96,7 @@
(define_predicate "add_operand"
(match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
{
- if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || GET_CODE (op) == SUBREG)
return add_reg_operand (op, mode);
return satisfies_constraint_L (op) || satisfies_constraint_CnL (op);
})
@@ -105,7 +105,7 @@
(define_predicate "arith_operand"
(match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
{
- if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode);
return satisfies_constraint_L (op);
})
diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c
index e31d4f1266d..59aee75bbf4 100644
--- a/gcc/config/fr30/fr30.c
+++ b/gcc/config/fr30/fr30.c
@@ -530,7 +530,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
case 'p':
/* Compute the register name of the second register in a hi/lo
register pair. */
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
output_operand_lossage ("fr30_print_operand: unrecognized %%p code");
else
fprintf (file, "r%d", REGNO (x) + 1);
@@ -642,7 +642,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
break;
case PLUS:
- if (GET_CODE (XEXP (x0, 0)) != REG
+ if (!REG_P (XEXP (x0, 0))
|| REGNO (XEXP (x0, 0)) < FRAME_POINTER_REGNUM
|| REGNO (XEXP (x0, 0)) > STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (x0, 1)))
@@ -848,7 +848,7 @@ fr30_check_multiple_regs (rtx *operands, int num_operands, int descending)
while (num_operands --)
{
- if (GET_CODE (operands [num_operands]) != REG)
+ if (!REG_P (operands [num_operands]))
return 0;
if (REGNO (operands [num_operands]) < prev_regno)
@@ -863,7 +863,7 @@ fr30_check_multiple_regs (rtx *operands, int num_operands, int descending)
while (num_operands --)
{
- if (GET_CODE (operands [num_operands]) != REG)
+ if (!REG_P (operands [num_operands]))
return 0;
if (REGNO (operands [num_operands]) > prev_regno)
@@ -930,7 +930,7 @@ fr30_move_double (rtx * operands)
rtx dest1 = operand_subword (dest, 1, TRUE, mode);
rtx new_mem;
- gcc_assert (GET_CODE (addr) == REG);
+ gcc_assert (REG_P (addr));
/* Copy the address before clobbering it. See PR 34174. */
emit_insn (gen_rtx_SET (dest1, addr));
@@ -960,7 +960,7 @@ fr30_move_double (rtx * operands)
rtx src0;
rtx src1;
- gcc_assert (GET_CODE (addr) == REG);
+ gcc_assert (REG_P (addr));
src0 = operand_subword (src, 0, TRUE, mode);
src1 = operand_subword (src, 1, TRUE, mode);
diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h
index 85cd49a2ed1..74451237c94 100644
--- a/gcc/config/fr30/fr30.h
+++ b/gcc/config/fr30/fr30.h
@@ -552,18 +552,18 @@ enum reg_class
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
do \
{ \
- if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
+ if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
&& ((MODE) == SImode || (MODE) == SFmode) \
- && GET_CODE (XEXP (X, 0)) == REG \
+ && REG_P (XEXP (X, 0)) \
&& REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
&& CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 << 6) - 4)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
&& ((MODE) == SImode || (MODE) == SFmode) \
- && GET_CODE (XEXP (X, 0)) == REG \
+ && REG_P (XEXP (X, 0)) \
&& REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
&& CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), -(1 << 9), (1 << 9) - 4)) \
@@ -574,18 +574,18 @@ enum reg_class
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
do \
{ \
- if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
+ if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
&& ((MODE) == SImode || (MODE) == SFmode) \
- && GET_CODE (XEXP (X, 0)) == REG \
+ && REG_P (XEXP (X, 0)) \
&& REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
&& CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 << 6) - 4)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
&& ((MODE) == SImode || (MODE) == SFmode) \
- && GET_CODE (XEXP (X, 0)) == REG \
+ && REG_P (XEXP (X, 0)) \
&& (REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
|| REGNO (XEXP (X, 0)) == ARG_POINTER_REGNUM) \
&& CONST_INT_P (XEXP (X, 1)) \
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index 5a369cfa249..b8670bbdb14 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -653,7 +653,7 @@
(match_operand:SI 2 "nonmemory_operand" "")))]
""
"{
- if ( GET_CODE (operands[2]) == REG
+ if ( REG_P (operands[2])
|| GET_CODE (operands[2]) == SUBREG)
emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
else if (!CONST_INT_P (operands[2]))
diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md
index 20873856906..f8b9b781e28 100644
--- a/gcc/config/fr30/predicates.md
+++ b/gcc/config/fr30/predicates.md
@@ -36,7 +36,7 @@
(match_code "reg")
{
return
- (GET_CODE (op) == REG
+ (REG_P (op)
&& REGNO (op) <= 15
&& REGNO (op) >= 8);
})
@@ -47,7 +47,7 @@
(match_code "reg")
{
return
- (GET_CODE (op) == REG
+ (REG_P (op)
&& REGNO (op) <= 7);
})
@@ -58,7 +58,7 @@
{
return (GET_CODE (op) == MEM
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == REG));
+ || REG_P (XEXP (op, 0))));
})
;; Returns TRUE if OP is a valid operand of a DImode operation.
@@ -116,7 +116,7 @@
(match_code "reg,const_int")
{
return
- (GET_CODE (op) == REG
+ (REG_P (op)
|| (CONST_INT_P (op)
&& INTVAL (op) >= -16
&& INTVAL (op) <= 15));
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index c3d9408f21b..72f867d3306 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -1448,7 +1448,7 @@ frv_function_prologue (FILE *file)
&& GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
{
rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
- if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
+ if (REG_P (address) && REGNO (address) == LR_REGNO)
SET_REGNO (address, GPR_FIRST + 3);
}
}
@@ -1611,8 +1611,8 @@ frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
/* We cannot use reg+reg addressing for DImode access. */
if (mode == DImode
&& GET_CODE (XEXP (mem, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
+ && REG_P (XEXP (XEXP (mem, 0), 0))
+ && REG_P (XEXP (XEXP (mem, 0), 1)))
{
rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
@@ -1645,8 +1645,8 @@ frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
/* Also we cannot use reg+reg addressing. */
if (GET_CODE (XEXP (mem, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
+ && REG_P (XEXP (XEXP (mem, 0), 0))
+ && REG_P (XEXP (XEXP (mem, 0), 1)))
{
rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
emit_move_insn (temp,
@@ -2564,7 +2564,7 @@ frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
fputs ("@(", stream);
if (!x0)
fputs (reg_names[GPR_R0], stream);
- else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
+ else if (REG_P (x0) || GET_CODE (x0) == SUBREG)
frv_print_operand_memory_reference_reg (stream, x0);
else
fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
@@ -2896,7 +2896,7 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'L':
/* Print the lower register of a double word register pair */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names[ REGNO (x)+1 ], file);
else
fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
@@ -2967,7 +2967,7 @@ frv_print_operand (FILE * file, rtx x, int code)
if (CONST_INT_P (x) && INTVAL (x) == 0)
fputs (reg_names[GPR_R0], file);
- else if (GET_CODE (x) == REG)
+ else if (REG_P (x))
fputs (reg_names [REGNO (x)], file);
else
@@ -2985,7 +2985,7 @@ frv_print_operand (FILE * file, rtx x, int code)
/* Fall through. */
case '\0':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names [REGNO (x)], file);
else if (CONST_INT_P (x)
@@ -3325,7 +3325,7 @@ frv_legitimate_address_p_1 (machine_mode mode,
case SUBREG:
x = SUBREG_REG (x);
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
break;
/* Fall through. */
@@ -3337,11 +3337,11 @@ frv_legitimate_address_p_1 (machine_mode mode,
case PRE_MODIFY:
x0 = XEXP (x, 0);
x1 = XEXP (x, 1);
- if (GET_CODE (x0) != REG
+ if (!REG_P (x0)
|| ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
|| GET_CODE (x1) != PLUS
|| ! rtx_equal_p (x0, XEXP (x1, 0))
- || GET_CODE (XEXP (x1, 1)) != REG
+ || !REG_P (XEXP (x1, 1))
|| ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
break;
@@ -3371,7 +3371,7 @@ frv_legitimate_address_p_1 (machine_mode mode,
if (GET_CODE (x0) == SUBREG)
x0 = SUBREG_REG (x0);
- if (GET_CODE (x0) != REG)
+ if (!REG_P (x0))
break;
regno0 = REGNO (x0);
@@ -3385,7 +3385,7 @@ frv_legitimate_address_p_1 (machine_mode mode,
case SUBREG:
x1 = SUBREG_REG (x1);
- if (GET_CODE (x1) != REG)
+ if (!REG_P (x1))
break;
/* Fall through. */
@@ -3969,7 +3969,7 @@ frv_emit_movsi (rtx dest, rtx src)
/* Virtual registers will almost always be replaced by an
add instruction, so expose this to CSE by copying to
an intermediate register. */
- || (GET_CODE (src) == REG
+ || (REG_P (src)
&& IN_RANGE (REGNO (src),
FIRST_VIRTUAL_REGISTER,
LAST_VIRTUAL_POINTER_REGISTER))))
@@ -4210,14 +4210,14 @@ output_move_single (rtx operands[], rtx insn)
rtx dest = operands[0];
rtx src = operands[1];
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int dest_regno = REGNO (dest);
machine_mode mode = GET_MODE (dest);
if (GPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* gpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4289,7 +4289,7 @@ output_move_single (rtx operands[], rtx insn)
else if (FPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* fpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4332,7 +4332,7 @@ output_move_single (rtx operands[], rtx insn)
else if (SPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* spr <- some sort of register */
int src_regno = REGNO (src);
@@ -4347,7 +4347,7 @@ output_move_single (rtx operands[], rtx insn)
else if (GET_CODE (dest) == MEM)
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int src_regno = REGNO (src);
machine_mode mode = GET_MODE (dest);
@@ -4425,13 +4425,13 @@ output_move_double (rtx operands[], rtx insn)
rtx src = operands[1];
machine_mode mode = GET_MODE (dest);
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int dest_regno = REGNO (dest);
if (GPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* gpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4465,7 +4465,7 @@ output_move_double (rtx operands[], rtx insn)
else if (FPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* fpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4506,7 +4506,7 @@ output_move_double (rtx operands[], rtx insn)
else if (GET_CODE (dest) == MEM)
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int src_regno = REGNO (src);
@@ -4555,14 +4555,14 @@ output_condmove_single (rtx operands[], rtx insn)
rtx dest = operands[2];
rtx src = operands[3];
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int dest_regno = REGNO (dest);
machine_mode mode = GET_MODE (dest);
if (GPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* gpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4600,7 +4600,7 @@ output_condmove_single (rtx operands[], rtx insn)
else if (FPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* fpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4631,7 +4631,7 @@ output_condmove_single (rtx operands[], rtx insn)
else if (GET_CODE (dest) == MEM)
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int src_regno = REGNO (src);
machine_mode mode = GET_MODE (dest);
@@ -4695,7 +4695,7 @@ frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
rtx cc_reg;
/* Floating point doesn't have comparison against a constant. */
- if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
+ if (GET_MODE (op0) == CC_FPmode && !REG_P (op1))
op1 = force_reg (GET_MODE (op0), op1);
/* Possibly disable using anything but a fixed register in order to work
@@ -5362,7 +5362,7 @@ frv_ifcvt_modify_tests (ce_if_block *ce_info, rtx *p_true, rtx *p_false)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int regno = REGNO (dest);
enum rtx_code src_code = GET_CODE (src);
@@ -5590,7 +5590,7 @@ frv_ifcvt_modify_multiple_tests (ce_if_block *ce_info,
if (!TARGET_MULTI_CE)
goto fail;
- if (GET_CODE (cr) != REG)
+ if (!REG_P (cr))
goto fail;
if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
@@ -5698,7 +5698,7 @@ frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
/* First search all registers currently loaded to see if we have an
applicable constant. */
if (CONSTANT_P (value)
- || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
+ || (REG_P (value) && REGNO (value) == LR_REGNO))
{
for (i = 0; i < num_alloc; i++)
{
@@ -5735,7 +5735,7 @@ frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
fprintf (dump_file, "Register %s will hold %ld\n",
reg_names[ REGNO (reg)], (long)INTVAL (value));
- else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
+ else if (REG_P (value) && REGNO (value) == LR_REGNO)
fprintf (dump_file, "Register %s will hold LR\n",
reg_names[ REGNO (reg)]);
@@ -5766,7 +5766,7 @@ frv_ifcvt_rewrite_mem (rtx mem, machine_mode mode, rtx insn)
rtx addr_op0 = XEXP (addr, 0);
rtx addr_op1 = XEXP (addr, 1);
- if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
+ if (REG_P (addr_op0) && CONSTANT_P (addr_op1))
{
rtx reg = frv_ifcvt_load_value (addr_op1, insn);
if (!reg)
@@ -5871,7 +5871,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
op1 = XEXP (test, 1);
test_reg = XEXP (op1, 0);
- if (GET_CODE (test_reg) != REG)
+ if (!REG_P (test_reg))
goto fail;
/* Is this the first nested if block in this sequence? If so, generate
@@ -6060,7 +6060,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
/* Remap a nested compare instruction to use the paired CC/CR reg. */
else if (ce_info->pass > 1
- && GET_CODE (dest) == REG
+ && REG_P (dest)
&& CC_P (REGNO (dest))
&& REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
&& TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
@@ -6310,7 +6310,7 @@ frv_secondary_reload_class (enum reg_class rclass,
case QUAD_REGS:
case GPR_REGS:
ret = NO_REGS;
- if (x && GET_CODE (x) == REG)
+ if (x && REG_P (x))
{
int regno = REGNO (x);
@@ -7027,7 +7027,7 @@ static int
frv_cond_flags (rtx cond)
{
gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
- && GET_CODE (XEXP (cond, 0)) == REG
+ && REG_P (XEXP (cond, 0))
&& CR_P (REGNO (XEXP (cond, 0)))
&& XEXP (cond, 1) == const0_rtx);
return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
@@ -7073,7 +7073,7 @@ frv_registers_conflict_p_1 (rtx pat, regstate_t cond)
FOR_EACH_SUBRTX_VAR (iter, array, pat, NONCONST)
{
rtx x = *iter;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
unsigned int regno;
FOR_EACH_REGNO (regno, x)
@@ -7137,7 +7137,7 @@ frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
{
unsigned int regno;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
FOR_EACH_REGNO (regno, x)
frv_packet.regstate[regno] |= *(regstate_t *) data;
@@ -7813,7 +7813,7 @@ frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
&& next_io->var_address != 0
&& next_membar != 0
&& GET_CODE (set) == SET
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
{
rtx src;
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index b33c272075a..d365476ef0a 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -6838,7 +6838,7 @@
"TARGET_MEDIA"
"
{
- if (GET_CODE (operands[0]) != REG || !ACC_P (REGNO (operands[0])))
+ if (!REG_P (operands[0]) || !ACC_P (REGNO (operands[0])))
FAIL;
operands[1] = frv_matching_accg_for_acc (operands[0]);
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index 02e5ce97789..c3724de35e6 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -27,13 +27,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_AP_OR_PSEUDO_P (REGNO (op));
@@ -53,7 +53,7 @@
rtx tmp = op;
if (GET_CODE (tmp) == SUBREG)
tmp = SUBREG_REG (tmp);
- if (GET_CODE (tmp) == REG
+ if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
op = reg_equiv_memory_loc (REGNO (tmp));
}
@@ -70,7 +70,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_OR_PSEUDO_P (REGNO (op));
@@ -88,13 +88,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -120,13 +120,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_OR_PSEUDO_P (REGNO (op));
@@ -148,13 +148,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -177,13 +177,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_OR_PSEUDO_P (REGNO (op));
@@ -202,13 +202,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_OR_PSEUDO_P (REGNO (op));
@@ -422,7 +422,7 @@
(define_predicate "lr_operand"
(match_code "reg")
{
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -562,7 +562,7 @@
if (!TARGET_FDPIC)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -581,7 +581,7 @@
{
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
return FALSE;
@@ -641,7 +641,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -658,7 +658,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -675,7 +675,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -695,7 +695,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -712,7 +712,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -729,7 +729,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -749,13 +749,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return FPR_OR_PSEUDO_P (REGNO (op));
@@ -773,13 +773,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -807,13 +807,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -842,13 +842,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -873,13 +873,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -905,13 +905,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -936,13 +936,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -967,13 +967,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -1011,7 +1011,7 @@
return FALSE;
addr = XEXP (op, 0);
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
addr_reg = addr;
else if (GET_CODE (addr) == PLUS)
@@ -1019,7 +1019,7 @@
rtx addr0 = XEXP (addr, 0);
rtx addr1 = XEXP (addr, 1);
- if (GET_CODE (addr0) != REG)
+ if (!REG_P (addr0))
return FALSE;
if (got12_operand (addr1, VOIDmode))
@@ -1237,7 +1237,7 @@
return FALSE;
op0 = XEXP (op, 0);
- if (GET_CODE (op0) != REG)
+ if (!REG_P (op0))
return FALSE;
regno = REGNO (op0);
@@ -1449,13 +1449,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return FPR_OR_PSEUDO_P (REGNO (op));
diff --git a/gcc/config/ft32/constraints.md b/gcc/config/ft32/constraints.md
index 6f2d49b3d4d..09a687e309a 100644
--- a/gcc/config/ft32/constraints.md
+++ b/gcc/config/ft32/constraints.md
@@ -65,7 +65,7 @@
(and (match_code "mem")
(match_test "ft32_is_mem_pm(op) && (
((GET_CODE (XEXP (op, 0)) == PLUS)) ||
- (GET_CODE (XEXP (op, 0)) == REG))"
+ (REG_P (XEXP (op, 0))))"
)))
(define_constraint "O"
diff --git a/gcc/config/ft32/ft32.c b/gcc/config/ft32/ft32.c
index 64b3172834f..d0f2ce262db 100644
--- a/gcc/config/ft32/ft32.c
+++ b/gcc/config/ft32/ft32.c
@@ -177,7 +177,7 @@ ft32_print_operand (FILE * file, rtx x, int code)
break;
case 'h':
- if (GET_CODE (operand) != REG)
+ if (!REG_P (operand))
internal_error ("%<h%> applied to non-register operand");
fprintf (file, "%s", reg_names[REGNO (operand) + 1]);
return;
@@ -878,7 +878,7 @@ ft32_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
rtx op1, op2;
op1 = XEXP (x, 0);
op2 = XEXP (x, 1);
- if (GET_CODE (op1) == REG
+ if (REG_P (op1)
&& CONST_INT_P (op2)
&& (-max_offset <= INTVAL (op2))
&& (INTVAL (op2) < max_offset)
diff --git a/gcc/config/ft32/ft32.md b/gcc/config/ft32/ft32.md
index 9e31f2ca7cb..174ef8d0bf7 100644
--- a/gcc/config/ft32/ft32.md
+++ b/gcc/config/ft32/ft32.md
@@ -747,7 +747,7 @@
""
"
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[0] = force_reg (SImode, operands[0]);
if (operands[1] != const0_rtx)
diff --git a/gcc/config/ft32/predicates.md b/gcc/config/ft32/predicates.md
index 89cf0b587b9..a77301f0b37 100644
--- a/gcc/config/ft32/predicates.md
+++ b/gcc/config/ft32/predicates.md
@@ -38,7 +38,7 @@
if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (op, 0), 0))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
return 1;
@@ -50,7 +50,7 @@
{
if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (op, 0), 0))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
return 1;
if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == SYMBOL_REF)
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index b4c5f228373..0006583b11e 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -1247,7 +1247,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
return gcn_address_register_p (x, SImode, strict);
else if (AS_FLAT_P (as) || AS_FLAT_SCRATCH_P (as))
{
- if (TARGET_GCN3 || GET_CODE (x) == REG)
+ if (TARGET_GCN3 || REG_P (x))
return ((GET_MODE_CLASS (mode) == MODE_VECTOR_INT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
? gcn_address_register_p (x, DImode, strict)
@@ -1281,7 +1281,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
{
gcc_assert (TARGET_GCN5_PLUS);
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
return (gcn_address_register_p (x, DImode, strict)
|| (!VECTOR_MODE_P (mode)
&& gcn_vec_address_register_p (x, DImode, strict)));
@@ -1345,9 +1345,9 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
rtx x1 = XEXP (x, 1);
if (!gcn_vec_address_register_p (x0, DImode, strict))
return false;
- if (GET_CODE (x1) == REG)
+ if (REG_P (x1))
{
- if (GET_CODE (x1) != REG
+ if (!REG_P (x1)
|| (REGNO (x1) <= FIRST_PSEUDO_REGISTER
&& !gcn_ssrc_register_operand (x1, DImode)))
return false;
@@ -5257,7 +5257,7 @@ print_operand_address (FILE *file, rtx mem)
}
else if (AS_ANY_FLAT_P (as))
{
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
print_reg (file, addr);
else
{
@@ -5352,7 +5352,7 @@ print_operand_address (FILE *file, rtx mem)
offset = XEXP (addr, 1);
print_reg (file, reg);
fprintf (file, ", ");
- if (GET_CODE (offset) == REG)
+ if (REG_P (offset))
print_reg (file, reg);
else if (CONST_INT_P (offset))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
@@ -5668,7 +5668,7 @@ print_operand (FILE *file, rtx x, int code)
return;
}
- if (GET_CODE (x0) == REG)
+ if (REG_P (x0))
return;
if (GET_CODE (x0) != PLUS)
{
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index d64eda8a5e0..44a4352f36a 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -755,7 +755,7 @@ h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
memindex = 0, regindex = 1, offset = (index + 1) * -4;
if (GET_CODE (x) == SET
- && GET_CODE (XEXP (x, regindex)) == REG
+ && REG_P (XEXP (x, regindex))
&& GET_CODE (XEXP (x, memindex)) == MEM
&& h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
return REGNO (XEXP (x, regindex));
@@ -1506,13 +1506,13 @@ h8300_print_operand (FILE *file, rtx x, int code)
fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
break;
case 'S':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fprintf (file, "%s", names_extended[REGNO (x)]);
else
goto def;
break;
case 'T':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fprintf (file, "%s", names_big[REGNO (x)]);
else
goto def;
@@ -1537,14 +1537,14 @@ h8300_print_operand (FILE *file, rtx x, int code)
break;
case 'R':
case 'X':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fprintf (file, "%s", byte_reg (x, 0));
else
goto def;
break;
case 'Y':
gcc_assert (bitint >= 0);
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
else
h8300_print_operand (file, x, 'R');
@@ -1827,7 +1827,7 @@ h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr)
fprintf (file, "(");
index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
- if (GET_CODE (index) == REG)
+ if (REG_P (index))
{
/* reg,foo */
h8300_print_operand_address (file, mode, XEXP (addr, 1));
@@ -2433,9 +2433,9 @@ h8300_bitfield_length (rtx op, rtx op2)
enum h8300_operand_class opclass;
unsigned int size, operand_length;
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
op = op2;
- gcc_assert (GET_CODE (op) != REG);
+ gcc_assert (!REG_P (op));
size = GET_MODE_SIZE (GET_MODE (op));
operand_length = h8300_classify_operand (op, size, &opclass);
@@ -2494,7 +2494,7 @@ h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
return (GET_CODE (addr) == inc_code
|| (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& h8300_displacement_length (addr, size) == 2));
}
@@ -2905,7 +2905,7 @@ compute_mov_length (rtx *operands)
in SImode and SFmode, the second mov.w involves an address
with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
only 2 bytes. */
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
return base_length - 2;
return base_length;
@@ -3013,13 +3013,13 @@ compute_mov_length (rtx *operands)
return base_length - 6;
/* @ERs and @ERd are 6 bytes shorter than the longest. */
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
return base_length - 6;
/* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
longest. */
if (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& CONST_INT_P (XEXP (addr, 1))
&& INTVAL (XEXP (addr, 1)) > -32768
&& INTVAL (XEXP (addr, 1)) < 32767)
@@ -3048,7 +3048,7 @@ output_plussi (rtx *operands)
if (TARGET_H8300)
{
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
if (CONST_INT_P (operands[2]))
@@ -3132,7 +3132,7 @@ compute_plussi_length (rtx *operands)
if (TARGET_H8300)
{
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
return 6;
if (CONST_INT_P (operands[2]))
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 5f3b98da929..1b495be4582 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -1832,7 +1832,7 @@
{
/* Force operand1 into a register if we're compiling
for the H8/300. */
- if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
+ if ((!REG_P (operands[2]) && operands[2] != const0_rtx)
&& TARGET_H8300)
operands[2] = force_reg (HImode, operands[2]);
h8300_expand_branch (operands);
@@ -2994,7 +2994,7 @@
|| GET_CODE (operands[3]) == MEM)
FAIL;
- if (GET_CODE (operands[3]) != REG)
+ if (!REG_P (operands[3]))
operands[3] = force_reg (HImode, operands[3]);
})
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index 14b0604ed64..5f30de3c80a 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -264,7 +264,7 @@
(define_predicate "jump_address_operand"
(match_code "reg,mem")
{
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
return GET_MODE (op) == Pmode;
if (GET_CODE (op) == MEM)
@@ -345,7 +345,7 @@
generation. This means that any named pattern which uses this predicate
must force its operands to match 'U' before emitting RTL. */
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
return 1;
if (GET_CODE (op) == SUBREG)
return 1;
@@ -369,7 +369,7 @@
(match_code "mem")
{
return (GET_CODE (op) == MEM
- && (GET_CODE (XEXP (op, 0)) == REG
+ && (REG_P (XEXP (op, 0))
|| CONST_INT_P (XEXP (op, 0))));
})
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index 0741c47bdb6..f6ab07de01b 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -269,7 +269,7 @@ ix86_expand_move (machine_mode mode, rtx operands[])
else
{
rtx temp = op0;
- if (GET_CODE (temp) != REG)
+ if (!REG_P (temp))
temp = gen_reg_rtx (Pmode);
temp = legitimize_pic_address (op1, temp);
if (temp == op0)
diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c
index 6ccd42a1874..fcac684f7b5 100644
--- a/gcc/config/i386/i386-features.c
+++ b/gcc/config/i386/i386-features.c
@@ -1200,7 +1200,7 @@ convertible_comparison_p (rtx_insn *insn)
gcc_assert (GET_CODE (src) == COMPARE);
- if (GET_CODE (dst) != REG
+ if (!REG_P (dst)
|| REGNO (dst) != FLAGS_REG
|| GET_MODE (dst) != CCZmode)
return false;
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index d36ded363c2..8a241915ee8 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1424,7 +1424,7 @@
rtx elt = XVECEXP (op, 0, i+1);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != V8SImode
|| REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
|| SET_SRC (elt) != CONST0_RTX (V8SImode))
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 6896b299ba1..a266f2a6fa8 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -914,7 +914,7 @@ ia64_load_pair_ok (rtx dst, rtx src)
/* ??? There is a thinko in the implementation of the "x" constraint and the
FP_REGS class. The constraint will also reject (reg f30:TI) so we must
also return false for it. */
- if (GET_CODE (dst) != REG
+ if (!REG_P (dst)
|| !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1)))
return 0;
if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
@@ -1116,7 +1116,7 @@ ia64_cannot_force_const_mem (machine_mode mode, rtx x)
bool
ia64_expand_load_address (rtx dest, rtx src)
{
- gcc_assert (GET_CODE (dest) == REG);
+ gcc_assert (REG_P (dest));
/* ILP32 mode still loads 64-bits of data from the GOT. This avoids
having to pointer-extend the value afterward. Other forms of address
@@ -1522,7 +1522,7 @@ ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
out[0] = adjust_automodify_address
(in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
- if (GET_CODE (XEXP (offset, 1)) == REG)
+ if (REG_P (XEXP (offset, 1)))
{
/* Can't adjust the postmodify to match. Emit the
original, then a separate addition insn. */
@@ -1590,7 +1590,7 @@ ia64_split_tmode_move (rtx operands[])
&& reg_overlap_mentioned_p (operands[0], operands[1]))
{
rtx base = XEXP (operands[1], 0);
- while (GET_CODE (base) != REG)
+ while (!REG_P (base))
base = XEXP (base, 0);
if (REGNO (base) == REGNO (operands[0]))
@@ -1604,7 +1604,7 @@ ia64_split_tmode_move (rtx operands[])
/* Another reason to do the moves in reversed order is if the first
element of the target register pair is also the second element of
the source register pair. */
- if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
+ if (REG_P (operands[0]) && REG_P (operands[1])
&& REGNO (operands[0]) == REGNO (operands[1]) + 1)
reversed = true;
@@ -1649,13 +1649,13 @@ spill_xfmode_rfmode_operand (rtx in, int force, machine_mode mode)
{
if (GET_CODE (in) == SUBREG
&& GET_MODE (SUBREG_REG (in)) == TImode
- && GET_CODE (SUBREG_REG (in)) == REG)
+ && REG_P (SUBREG_REG (in)))
{
rtx memt = assign_stack_temp (TImode, 16);
emit_move_insn (memt, SUBREG_REG (in));
return adjust_address (memt, mode, 0);
}
- else if (force && GET_CODE (in) == REG)
+ else if (force && REG_P (in))
{
rtx memx = assign_stack_temp (mode, 16);
emit_move_insn (memx, in);
@@ -1684,7 +1684,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
for the last case. This case does not happen for stdarg/vararg routines,
because we do a block store to memory of unnamed arguments. */
- if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
+ if (REG_P (op0) && GR_REGNO_P (REGNO (op0)))
{
rtx out[2];
@@ -1695,7 +1695,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
/* Struct to register can just use TImode instead. */
if ((GET_CODE (operands[1]) == SUBREG
&& GET_MODE (SUBREG_REG (operands[1])) == TImode)
- || (GET_CODE (operands[1]) == REG
+ || (REG_P (operands[1])
&& GR_REGNO_P (REGNO (operands[1]))))
{
rtx op1 = operands[1];
@@ -1736,7 +1736,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
return true;
}
- if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
+ if (REG_P (operands[1]) && GR_REGNO_P (REGNO (operands[1])))
{
/* We're hoping to transform everything that deals with XFmode
quantities and GR registers early in the compiler. */
@@ -1773,7 +1773,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
{
operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
- if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
+ if (GET_MODE (op0) == TImode && REG_P (op0))
{
rtx memt, memx, in = operands[1];
if (CONSTANT_P (in))
@@ -5441,7 +5441,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
str = reg_names [FR_REG (1)];
else
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
str = reg_names [REGNO (x)];
}
fputs (str, file);
@@ -5499,7 +5499,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
value = INTVAL (x);
else
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
fprintf (file, ", %s", reg_names[REGNO (x)]);
return;
}
@@ -5570,7 +5570,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
case 'r':
/* If this operand is the constant zero, write it as register zero.
Any register, zero, or CONST_INT value is OK here. */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names[REGNO (x)], file);
else if (x == CONST0_RTX (GET_MODE (x)))
fputs ("r0", file);
@@ -5898,7 +5898,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
{
int regno = -1;
- if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || GET_CODE (x) == SUBREG)
regno = true_regnum (x);
switch (rclass)
@@ -6602,7 +6602,7 @@ rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
if (GET_CODE (cond) == EQ)
is_complemented = 1;
cond = XEXP (cond, 0);
- gcc_assert (GET_CODE (cond) == REG
+ gcc_assert (REG_P (cond)
&& REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
pred = REGNO (cond);
if (is_complemented)
@@ -6722,7 +6722,7 @@ rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
/* Operators with side-effects. */
case POST_INC: case POST_DEC:
- gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
+ gcc_assert (REG_P (XEXP (x, 0)));
new_flags.is_write = 0;
need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
@@ -6731,7 +6731,7 @@ rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
break;
case POST_MODIFY:
- gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
+ gcc_assert (REG_P (XEXP (x, 0)));
new_flags.is_write = 0;
need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
@@ -9628,7 +9628,7 @@ ia64_st_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
gcc_assert (reg);
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
- gcc_assert (GET_CODE (reg) == REG);
+ gcc_assert (REG_P (reg));
dest = ia64_single_set (consumer);
gcc_assert (dest);
@@ -9652,7 +9652,7 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
gcc_assert (reg);
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
- gcc_assert (GET_CODE (reg) == REG);
+ gcc_assert (REG_P (reg));
src = ia64_single_set (consumer);
gcc_assert (src);
@@ -10171,7 +10171,7 @@ process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind)
rtx base;
gcc_assert (MEM_P (dest));
- if (GET_CODE (XEXP (dest, 0)) == REG)
+ if (REG_P (XEXP (dest, 0)))
{
base = XEXP (dest, 0);
off = 0;
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 5d55b190334..5322e66e1be 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -250,8 +250,8 @@
[(set (match_operand:CCI 0 "register_operand" "")
(match_operand:CCI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && GR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(set (match_dup 2) (const_int 0))
(cond_exec (ne (match_dup 3) (const_int 0))
(set (match_dup 2) (const_int 1)))]
@@ -280,8 +280,8 @@
[(set (match_operand:BI 0 "register_operand" "")
(match_operand:BI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && GR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(cond_exec (ne (match_dup 1) (const_int 0))
(set (match_dup 0) (const_int 1)))
(cond_exec (eq (match_dup 1) (const_int 0))
@@ -292,8 +292,8 @@
[(set (match_operand:BI 0 "register_operand" "")
(match_operand:BI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))
(set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
@@ -1570,8 +1570,8 @@
tbit.nz.and.orcm %0, %I0 = %2, 0
and %0 = %2, %1"
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[2]) && PR_REGNO_P (REGNO (operands[2]))"
[(cond_exec (eq (match_dup 2) (const_int 0))
(set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
(match_dup 0))))]
@@ -1588,8 +1588,8 @@
tbit.z.and.orcm %0, %I0 = %1, 0
andcm %0 = %2, %1"
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(cond_exec (ne (match_dup 1) (const_int 0))
(set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
(match_dup 0))))]
@@ -1606,8 +1606,8 @@
tbit.nz.or.andcm %0, %I0 = %2, 0
or %0 = %2, %1"
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[2]) && PR_REGNO_P (REGNO (operands[2]))"
[(cond_exec (ne (match_dup 2) (const_int 0))
(set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
(match_dup 0))))]
@@ -1623,8 +1623,8 @@
#
tbit.z.or.andcm %0, %I0 = %1, 0"
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(cond_exec (eq (match_dup 1) (const_int 0))
(set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
(match_dup 0))))]
@@ -1648,7 +1648,7 @@
(not:BI (match_operand:BI 1 "register_operand" "")))
(clobber (match_scratch:BI 2 ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
&& rtx_equal_p (operands[0], operands[1])"
[(set (match_dup 4) (match_dup 3))
(set (match_dup 0) (const_int 1))
@@ -1663,8 +1663,8 @@
(not:BI (match_operand:BI 1 "register_operand" "")))
(clobber (match_scratch:BI 2 ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))
&& ! rtx_equal_p (operands[0], operands[1])"
[(cond_exec (ne (match_dup 1) (const_int 0))
(set (match_dup 0) (const_int 0)))
@@ -5108,12 +5108,12 @@
rtx bsp = gen_rtx_REG (Pmode, 10);
rtx sp = gen_rtx_REG (Pmode, 9);
- if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
+ if (!REG_P (operands[0]) || REGNO (operands[0]) != 10)
{
emit_move_insn (bsp, operands[0]);
operands[0] = bsp;
}
- if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
+ if (!REG_P (operands[2]) || REGNO (operands[2]) != 9)
{
emit_move_insn (sp, operands[2]);
operands[2] = sp;
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index f3a34865055..4a539cdf423 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -310,7 +310,7 @@
(and (match_operand 0 "nonimmediate_operand")
(match_test "GET_CODE (op) != MEM
|| GET_CODE (XEXP (op, 0)) != POST_MODIFY
- || GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) != REG")))
+ || !REG_P (XEXP (XEXP (XEXP (op, 0), 1), 1))")))
;; Like destination_operand, but don't allow any post-increments.
(define_predicate "not_postinc_destination_operand"
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index fd290d096ae..b5e2754dc3e 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -334,7 +334,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
while (GET_CODE (xinsn) == SUBREG)
xinsn = SUBREG_REG (xinsn);
- if (GET_CODE (xinsn) == REG
+ if (REG_P (xinsn)
&& iq2000_reg_mode_ok_for_base_p (xinsn, mode, strict))
return 1;
@@ -345,7 +345,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
while (GET_CODE (xlow0) == SUBREG)
xlow0 = SUBREG_REG (xlow0);
- if (GET_CODE (xlow0) == REG
+ if (REG_P (xlow0)
&& iq2000_reg_mode_ok_for_base_p (xlow0, mode, strict)
&& iq2000_check_split (xlow1, mode))
return 1;
@@ -728,7 +728,7 @@ iq2000_move_1word (rtx operands[], rtx_insn *insn, int unsignedp)
rtx add_op0 = XEXP (op1, 0);
rtx add_op1 = XEXP (op1, 1);
- if (GET_CODE (XEXP (op1, 1)) == REG
+ if (REG_P (XEXP (op1, 1))
&& CONST_INT_P (XEXP (op1, 0)))
add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
@@ -842,10 +842,10 @@ iq2000_address_cost (rtx addr, machine_mode mode, addr_space_t as,
rtx plus0 = XEXP (addr, 0);
rtx plus1 = XEXP (addr, 1);
- if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
+ if (!REG_P (plus0) && REG_P (plus1))
plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
- if (GET_CODE (plus0) != REG)
+ if (!REG_P (plus0))
break;
switch (GET_CODE (plus1))
@@ -956,7 +956,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
branch_p = (result == 0);
if (branch_p)
{
- if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
+ if (REG_P (cmp0) || GET_CODE (cmp0) == SUBREG)
{
/* Comparisons against zero are simple branches. */
if (CONST_INT_P (cmp1) && INTVAL (cmp1) == 0)
@@ -1991,7 +1991,7 @@ iq2000_expand_prologue (void)
{
int words;
- gcc_assert (GET_CODE (entry_parm) == REG);
+ gcc_assert (REG_P (entry_parm));
/* Passed in a register, so will get homed automatically. */
if (GET_MODE (entry_parm) == BLKmode)
@@ -2961,7 +2961,7 @@ iq2000_print_operand_address (FILE * file, machine_mode mode, rtx addr)
rtx arg0 = XEXP (addr, 0);
rtx arg1 = XEXP (addr, 1);
- if (GET_CODE (arg0) != REG)
+ if (!REG_P (arg0))
abort_with_insn (addr,
"PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
@@ -2978,15 +2978,15 @@ iq2000_print_operand_address (FILE * file, machine_mode mode, rtx addr)
rtx arg0 = XEXP (addr, 0);
rtx arg1 = XEXP (addr, 1);
- if (GET_CODE (arg0) == REG)
+ if (REG_P (arg0))
{
reg = arg0;
offset = arg1;
- if (GET_CODE (offset) == REG)
+ if (REG_P (offset))
abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
}
- else if (GET_CODE (arg1) == REG)
+ else if (REG_P (arg1))
reg = arg1, offset = arg0;
else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
{
@@ -3255,7 +3255,7 @@ iq2000_print_operand (FILE *file, rtx op, int letter)
else if (letter == 't')
fputs (code == EQ ? "t" : "f", file);
- else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
+ else if (code == CONST && REG_P (XEXP (op, 0)))
{
iq2000_print_operand (file, XEXP (op, 0), letter);
}
diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md
index fac0f65159d..0ff9d01998a 100644
--- a/gcc/config/iq2000/iq2000.md
+++ b/gcc/config/iq2000/iq2000.md
@@ -1306,7 +1306,7 @@
""
"*
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
return \"j\\t%0\";
return \"j\\t%l0\";
/* return \"b\\t%l0\";*/
@@ -1324,7 +1324,7 @@
if (operands[0]) /* eliminate unused code warnings */
{
dest = operands[0];
- if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
+ if (!REG_P (dest) || GET_MODE (dest) != Pmode)
operands[0] = copy_to_mode_reg (Pmode, dest);
if (!(Pmode == DImode))
@@ -1511,7 +1511,7 @@
if (operands[0]) /* eliminate unused code warnings */
{
addr = XEXP (operands[0], 0);
- if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
+ if ((!REG_P (addr) && (!CONSTANT_ADDRESS_P (addr)))
|| ! call_insn_operand (addr, VOIDmode))
XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
@@ -1581,7 +1581,7 @@
if (operands[0]) /* eliminate unused code warning */
{
addr = XEXP (operands[1], 0);
- if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
+ if ((!REG_P (addr) && (!CONSTANT_ADDRESS_P (addr)))
|| ! call_insn_operand (addr, VOIDmode))
XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md
index 93fa4737648..c8f4ef37fc8 100644
--- a/gcc/config/iq2000/predicates.md
+++ b/gcc/config/iq2000/predicates.md
@@ -139,12 +139,12 @@
case PLUS:
plus0 = XEXP (addr, 0);
plus1 = XEXP (addr, 1);
- if (GET_CODE (plus0) == REG
+ if (REG_P (plus0)
&& CONST_INT_P (plus1) && SMALL_INT (plus1)
&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
return 1;
- else if (GET_CODE (plus1) == REG
+ else if (REG_P (plus1)
&& CONST_INT_P (plus0) && SMALL_INT (plus0)
&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
return 1;
@@ -205,7 +205,7 @@
(match_code "const_int,const,symbol_ref,reg")
{
return (CONSTANT_ADDRESS_P (op)
- || (GET_CODE (op) == REG && op != arg_pointer_rtx
+ || (REG_P (op) && op != arg_pointer_rtx
&& ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
&& REGNO (op) <= LAST_VIRTUAL_REGISTER)));
})
diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c
index 294f0f46439..13ad0bf65d7 100644
--- a/gcc/config/lm32/lm32.c
+++ b/gcc/config/lm32/lm32.c
@@ -579,7 +579,7 @@ lm32_print_operand_address (FILE * file, rtx addr)
rtx arg0 = XEXP (addr, 0);
rtx arg1 = XEXP (addr, 1);
- if (GET_CODE (arg0) == REG && CONSTANT_P (arg1))
+ if (REG_P (arg0) && CONSTANT_P (arg1))
{
if (CONST_INT_P (arg1))
fprintf (file, "(%s+%ld)", reg_names[REGNO (arg0)],
@@ -1055,7 +1055,7 @@ lm32_rtx_costs (rtx x, machine_mode mode, int outer_code,
*total = COSTS_N_INSNS (2 + 1 + cycles);
return true;
}
- else if (GET_CODE (XEXP (x, 1)) == REG)
+ else if (REG_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (1 + GET_MODE_SIZE (mode) / 2);
return true;
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index 9c8a72e2a17..095a9a6818f 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -318,7 +318,7 @@
(define_insn "*extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
+ "TARGET_SIGN_EXTEND_ENABLED || (!REG_P (operands[1]))"
"@
lb %0, %1
sextb %0, %1"
@@ -338,7 +338,7 @@
(define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
+ "TARGET_SIGN_EXTEND_ENABLED || (!REG_P (operands[1]))"
"@
lb %0, %1
sextb %0, %1"
@@ -358,7 +358,7 @@
(define_insn "*extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
+ "TARGET_SIGN_EXTEND_ENABLED || (!REG_P (operands[1]))"
"@
lh %0, %1
sexth %0, %1"
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 08e0542bd2b..1ff54b41363 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -123,10 +123,10 @@ static GTY(()) rtx patternr[30];
/* Some macros to simplify the logic throughout this file. */
#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
-#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
+#define IS_MEM_REG(rtx) (REG_P (rtx) && IS_MEM_REGNO (REGNO (rtx)))
#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
-#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
+#define IS_CR_REG(rtx) (REG_P (rtx) && IS_CR_REGNO (REGNO (rtx)))
static int
far_addr_space_p (rtx x)
@@ -176,7 +176,7 @@ encode_pattern_1 (rtx x)
GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
*patternp++ = 'S';
if (GET_MODE (x) == PSImode
- && GET_CODE (XEXP (x, 0)) == REG)
+ && REG_P (XEXP (x, 0)))
*patternp++ = 'S';
encode_pattern_1 (XEXP (x, 0));
break;
@@ -757,7 +757,7 @@ m32c_secondary_reload_class (int rclass, machine_mode mode, rtx x)
&& GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
return QI_REGS;
if (reg_classes_intersect_p (rclass, CR_REGS)
- && GET_CODE (x) == REG
+ && REG_P (x)
&& REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
return (TARGET_A16 || mode == HImode) ? HI_REGS : A_REGS;
return NO_REGS;
@@ -836,12 +836,12 @@ m32c_can_change_mode_class (machine_mode from,
/* Helpers for the rest of the file. */
/* TRUE if the rtx is a REG rtx for the given register. */
-#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
+#define IS_REG(rtx,regno) (REG_P (rtx) \
&& REGNO (rtx) == regno)
/* TRUE if the rtx is a pseudo - specifically, one we can use as a
base register in address calculations (hence the "strict"
argument). */
-#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
+#define IS_PSEUDO(rtx,strict) (!strict && REG_P (rtx) \
&& (REGNO (rtx) == AP_REGNO \
|| REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
@@ -1672,7 +1672,7 @@ m32c_legitimate_address_p (machine_mode mode, rtx x, bool strict)
if (GET_CODE (x) == PRE_DEC
|| GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
{
- return (GET_CODE (XEXP (x, 0)) == REG
+ return (REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == SP_REGNO);
}
@@ -1784,7 +1784,7 @@ m32c_legitimate_address_p (machine_mode mode, rtx x, bool strict)
int
m32c_reg_ok_for_base_p (rtx x, int strict)
{
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
return 0;
switch (REGNO (x))
{
@@ -1844,7 +1844,7 @@ m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
#endif
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == FB_REGNO
&& CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) < -128
@@ -1883,7 +1883,7 @@ m32c_legitimize_reload_address (rtx * x,
The code below is a second attempt at the above. */
if (GET_CODE (*x) == PLUS
- && GET_CODE (XEXP (*x, 0)) == REG
+ && REG_P (XEXP (*x, 0))
&& REGNO (XEXP (*x, 0)) == FB_REGNO
&& CONST_INT_P (XEXP (*x, 1))
&& (INTVAL (XEXP (*x, 1)) < -128
@@ -1906,7 +1906,7 @@ m32c_legitimize_reload_address (rtx * x,
if (GET_CODE (*x) == PLUS
&& GET_CODE (XEXP (*x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (*x, 0), 0))
&& REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
&& CONST_INT_P (XEXP (XEXP (*x, 0), 1))
&& CONST_INT_P (XEXP (*x, 1))
@@ -2070,7 +2070,7 @@ m32c_addr_space_legitimize_address (rtx x, rtx oldx, machine_mode mode,
fprintf (stderr, "\n");
#endif
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
{
x = force_reg (SImode, x);
}
@@ -2572,7 +2572,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
if (code == 'H' && GET_MODE (x) == HImode)
{
/* We can't actually represent this as an rtx. Do it here. */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
switch (REGNO (x))
{
@@ -2593,7 +2593,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
/* This is for BMcond, which always wants word register names. */
if (code == 'h' && GET_MODE (x) == QImode)
{
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
x = gen_rtx_REG (HImode, REGNO (x));
code = 0;
}
@@ -2678,7 +2678,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
entire address range. */
rtx base =
patternr[conversions[i].format[j + 2] - '0'];
- if (GET_CODE (base) == REG)
+ if (REG_P (base))
switch (REGNO (base))
{
case A0_REGNO:
@@ -2751,7 +2751,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
if (ISDIGIT (conversions[i].format[k]))
{
rtx reg = patternr[conversions[i].format[k] - '0'];
- if (GET_CODE (reg) == REG
+ if (REG_P (reg)
&& (REGNO (reg) == SB_REGNO
|| REGNO (reg) == FB_REGNO
|| REGNO (reg) == SP_REGNO))
@@ -2813,7 +2813,7 @@ m32c_print_operand_address (FILE * stream, machine_mode /*mode*/, rtx address)
address = XEXP (address, 0);
else
/* cf: gcc.dg/asm-4.c. */
- gcc_assert (GET_CODE (address) == REG);
+ gcc_assert (REG_P (address));
m32c_print_operand (stream, address, 0);
}
@@ -3148,7 +3148,7 @@ m32c_illegal_subreg_p (rtx op)
if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
return false;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return false;
if (REGNO (op) >= MEM0_REGNO)
return false;
@@ -3266,7 +3266,7 @@ m32c_subreg (machine_mode outer,
|| GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
{
rtx r = simplify_gen_subreg (outer, x, inner, byte);
if (GET_CODE (r) == SUBREG
@@ -3545,7 +3545,7 @@ m32c_expand_setmemhi(rtx *operands)
desto = gen_reg_rtx (Pmode);
counto = gen_reg_rtx (HImode);
- if (GET_CODE (desta) != REG
+ if (!REG_P (desta)
|| REGNO (desta) < FIRST_PSEUDO_REGISTER)
desta = copy_to_mode_reg (Pmode, desta);
@@ -3571,11 +3571,11 @@ m32c_expand_setmemhi(rtx *operands)
}
/* This is the generalized memset() case. */
- if (GET_CODE (val) != REG
+ if (!REG_P (val)
|| REGNO (val) < FIRST_PSEUDO_REGISTER)
val = copy_to_mode_reg (QImode, val);
- if (GET_CODE (count) != REG
+ if (!REG_P (count)
|| REGNO (count) < FIRST_PSEUDO_REGISTER)
count = copy_to_mode_reg (HImode, count);
@@ -3605,11 +3605,11 @@ m32c_expand_cpymemhi(rtx *operands)
srco = gen_reg_rtx (Pmode);
counto = gen_reg_rtx (HImode);
- if (GET_CODE (desta) != REG
+ if (!REG_P (desta)
|| REGNO (desta) < FIRST_PSEUDO_REGISTER)
desta = copy_to_mode_reg (Pmode, desta);
- if (GET_CODE (srca) != REG
+ if (!REG_P (srca)
|| REGNO (srca) < FIRST_PSEUDO_REGISTER)
srca = copy_to_mode_reg (Pmode, srca);
@@ -3627,7 +3627,7 @@ m32c_expand_cpymemhi(rtx *operands)
}
/* This is the generalized memset() case. */
- if (GET_CODE (count) != REG
+ if (!REG_P (count)
|| REGNO (count) < FIRST_PSEUDO_REGISTER)
count = copy_to_mode_reg (HImode, count);
@@ -3656,11 +3656,11 @@ m32c_expand_movstr(rtx *operands)
desto = gen_reg_rtx (Pmode);
srco = gen_reg_rtx (Pmode);
- if (GET_CODE (desta) != REG
+ if (!REG_P (desta)
|| REGNO (desta) < FIRST_PSEUDO_REGISTER)
desta = copy_to_mode_reg (Pmode, desta);
- if (GET_CODE (srca) != REG
+ if (!REG_P (srca)
|| REGNO (srca) < FIRST_PSEUDO_REGISTER)
srca = copy_to_mode_reg (Pmode, srca);
@@ -3683,11 +3683,11 @@ m32c_expand_cmpstr(rtx *operands)
src1a = XEXP (operands[1], 0);
src2a = XEXP (operands[2], 0);
- if (GET_CODE (src1a) != REG
+ if (!REG_P (src1a)
|| REGNO (src1a) < FIRST_PSEUDO_REGISTER)
src1a = copy_to_mode_reg (Pmode, src1a);
- if (GET_CODE (src2a) != REG
+ if (!REG_P (src2a)
|| REGNO (src2a) < FIRST_PSEUDO_REGISTER)
src2a = copy_to_mode_reg (Pmode, src2a);
@@ -3980,7 +3980,7 @@ const char *
m32c_scc_pattern(rtx *operands, RTX_CODE code)
{
static char buf[30];
- if (GET_CODE (operands[0]) == REG
+ if (REG_P (operands[0])
&& REGNO (operands[0]) == R0_REGNO)
{
if (code == EQ)
@@ -4376,7 +4376,7 @@ m32c_compare_redundant (rtx_insn *cmp, rtx *operands)
/* Check for PREV changing a register that's used to compute a
value in CMP, even if it doesn't otherwise change flags. */
- if (GET_CODE (operands[0]) == REG
+ if (REG_P (operands[0])
&& rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[0]))
{
#if DEBUG_CMP
@@ -4385,7 +4385,7 @@ m32c_compare_redundant (rtx_insn *cmp, rtx *operands)
#endif
return false;
}
- if (GET_CODE (operands[1]) == REG
+ if (REG_P (operands[1])
&& rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[1]))
{
#if DEBUG_CMP
@@ -4403,7 +4403,7 @@ m32c_compare_redundant (rtx_insn *cmp, rtx *operands)
#endif
if (GET_CODE (pp) == SET
- && GET_CODE (XEXP (pp, 0)) == REG
+ && REG_P (XEXP (pp, 0))
&& REGNO (XEXP (pp, 0)) == FLG_REGNO
&& GET_CODE (XEXP (pp, 1)) == COMPARE)
{
diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md
index 93cd9173f75..2c66da5f284 100644
--- a/gcc/config/m32c/predicates.md
+++ b/gcc/config/m32c/predicates.md
@@ -46,7 +46,7 @@
(ior (and (match_code "reg")
(match_test "REGNO(op) >= FIRST_PSEUDO_REGISTER"))
(and (match_code "subreg")
- (and (match_test "GET_CODE (XEXP (op, 0)) == REG")
+ (and (match_test "REG_P (XEXP (op, 0))")
(match_test "REGNO(XEXP (op,0)) >= FIRST_PSEUDO_REGISTER")))))
@@ -197,7 +197,7 @@
rtx reg = XEXP (op, 0);
rtx size = XEXP (op, 1);
rtx pos = XEXP (op, 2);
- return (GET_CODE (reg) == REG
+ return (REG_P (reg)
&& REGNO (reg) == R1_REGNO
&& CONST_INT_P (size)
&& INTVAL (size) == 8
@@ -229,7 +229,7 @@
(ior (match_test "REGNO(op) == R2_REGNO")
(match_test "REGNO(op) == R3_REGNO")))
(and (match_code "subreg")
- (match_test "GET_CODE (XEXP (op, 0)) == REG && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)"))))
+ (match_test "REG_P (XEXP (op, 0)) && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)"))))
; Likewise, plus TRUE for a0..a1.
(define_predicate "m32c_r2r3a_operand"
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 4f757403f7e..5c02c6eb3df 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -1541,8 +1541,8 @@ m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
}
if (ch)
{
- if (GET_CODE (XEXP (x, 1)) == REG
- && GET_CODE (XEXP (x, 0)) == REG)
+ if (REG_P (XEXP (x, 1))
+ && REG_P (XEXP (x, 0)))
{
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
{
@@ -1554,9 +1554,9 @@ m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
if (memory_address_p (mode, x))
return x;
}
- if (GET_CODE (XEXP (x, 0)) == REG
+ if (REG_P (XEXP (x, 0))
|| (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (x, 0), 0))
&& GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode))
{
rtx temp = gen_reg_rtx (Pmode);
@@ -1565,12 +1565,12 @@ m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
COPY_ONCE (x);
XEXP (x, 1) = temp;
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
- && GET_CODE (XEXP (x, 0)) == REG)
+ && REG_P (XEXP (x, 0)))
x = force_operand (x, 0);
}
- else if (GET_CODE (XEXP (x, 1)) == REG
+ else if (REG_P (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
- && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
+ && REG_P (XEXP (XEXP (x, 1), 0))
&& GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode))
{
rtx temp = gen_reg_rtx (Pmode);
@@ -1579,7 +1579,7 @@ m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
COPY_ONCE (x);
XEXP (x, 0) = temp;
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
- && GET_CODE (XEXP (x, 1)) == REG)
+ && REG_P (XEXP (x, 1)))
x = force_operand (x, 0);
}
}
@@ -1671,7 +1671,7 @@ output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
/* The m68k cmp.l instruction requires operand1 to be a reg as used
below. Swap the operands and change the op if these requirements
are not fulfilled. */
- if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
+ if (REG_P (operand2) && !REG_P (operand1))
{
rtx tmp = operand1;
@@ -1680,14 +1680,14 @@ output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
op_code = swap_condition (op_code);
}
loperands[0] = operand1;
- if (GET_CODE (operand1) == REG)
+ if (REG_P (operand1))
loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
else
loperands[1] = adjust_address (operand1, SImode, 4);
if (operand2 != const0_rtx)
{
loperands[2] = operand2;
- if (GET_CODE (operand2) == REG)
+ if (REG_P (operand2))
loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
else
loperands[3] = adjust_address (operand2, SImode, 4);
@@ -2883,9 +2883,9 @@ m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
case PLUS:
/* An lea costs about three times as much as a simple add. */
if (mode == SImode
- && GET_CODE (XEXP (x, 1)) == REG
+ && REG_P (XEXP (x, 1))
&& GET_CODE (XEXP (x, 0)) == MULT
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
|| INTVAL (XEXP (XEXP (x, 0), 1)) == 4
@@ -3681,12 +3681,12 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
register rtx tem;
if (scratch_reg
- && reload_in_progress && GET_CODE (operand0) == REG
+ && reload_in_progress && REG_P (operand0)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
operand0 = reg_equiv_mem (REGNO (operand0));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand0) == SUBREG
- && GET_CODE (SUBREG_REG (operand0)) == REG
+ && REG_P (SUBREG_REG (operand0))
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
@@ -3698,12 +3698,12 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
}
if (scratch_reg
- && reload_in_progress && GET_CODE (operand1) == REG
+ && reload_in_progress && REG_P (operand1)
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
operand1 = reg_equiv_mem (REGNO (operand1));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand1) == SUBREG
- && GET_CODE (SUBREG_REG (operand1)) == REG
+ && REG_P (SUBREG_REG (operand1))
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
@@ -4062,9 +4062,9 @@ find_addr_reg (rtx addr)
{
while (GET_CODE (addr) == PLUS)
{
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
addr = XEXP (addr, 0);
- else if (GET_CODE (XEXP (addr, 1)) == REG)
+ else if (REG_P (XEXP (addr, 1)))
addr = XEXP (addr, 1);
else if (CONSTANT_P (XEXP (addr, 0)))
addr = XEXP (addr, 1);
@@ -4073,7 +4073,7 @@ find_addr_reg (rtx addr)
else
gcc_unreachable ();
}
- gcc_assert (GET_CODE (addr) == REG);
+ gcc_assert (REG_P (addr));
return addr;
}
@@ -4097,7 +4097,7 @@ output_addsi3 (rtx *operands)
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
return "move%.l %2,%0\n\tadd%.l %1,%0";
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
}
@@ -4183,7 +4183,7 @@ notice_update_cc (rtx exp, rtx insn)
else if (!FP_REG_P (SET_DEST (exp))
&& !FP_REG_P (SET_SRC (exp))
&& GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
- && (GET_CODE (SET_SRC (exp)) == REG
+ && (REG_P (SET_SRC (exp))
|| GET_CODE (SET_SRC (exp)) == MEM
|| CONST_DOUBLE_P (SET_SRC (exp))))
CC_STATUS_INIT;
@@ -4240,7 +4240,7 @@ notice_update_cc (rtx exp, rtx insn)
default:
break;
}
- if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
+ if (cc_status.value1 && REG_P (cc_status.value1)
&& cc_status.value2
&& reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
cc_status.value2 = 0;
@@ -4489,7 +4489,7 @@ print_operand (FILE *file, rtx op, int letter)
if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
fprintf (file, "@PLTPC");
}
- else if (GET_CODE (op) == REG)
+ else if (REG_P (op))
{
if (letter == 'R')
/* Print out the second register name of a register pair.
@@ -4862,7 +4862,7 @@ strict_low_part_peephole_ok (machine_mode mode, rtx_insn *first_insn,
&& SET_SRC (set) == const0_rtx)
return true;
else if (GET_CODE (dest) == STRICT_LOW_PART
- && GET_CODE (XEXP (dest, 0)) == REG
+ && REG_P (XEXP (dest, 0))
&& REGNO (XEXP (dest, 0)) == REGNO (target)
&& (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
<= GET_MODE_SIZE (mode)))
@@ -4944,7 +4944,7 @@ output_andsi3 (rtx *operands)
|| offsettable_memref_p (operands[0]))
&& !TARGET_COLDFIRE)
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[0] = adjust_address (operands[0], HImode, 2);
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
@@ -4982,7 +4982,7 @@ output_iorsi3 (rtx *operands)
|| offsettable_memref_p (operands[0]))
&& !TARGET_COLDFIRE)
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[0] = adjust_address (operands[0], HImode, 2);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
CC_STATUS_INIT;
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 4ed3111c439..ce4f39c953b 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -1581,7 +1581,7 @@
(match_operand:SI 1 "general_src_operand" "doJS,i")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
{
/* Must clear condition codes, since the move.l bases them on
the entire 32 bits, not just the desired 8 bits. */
@@ -1599,7 +1599,7 @@
(match_operand:HI 1 "general_src_operand" "doJS,i")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[0]) == REG
+ if (REG_P (operands[0])
&& (GET_CODE (operands[1]) == MEM
|| CONST_INT_P (operands[1])))
{
@@ -1608,7 +1608,7 @@
CC_STATUS_INIT;
return "move%.w %1,%0";
}
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
{
/* Must clear condition codes, since the move.l bases them on
the entire 32 bits, not just the desired 8 bits. */
@@ -1626,7 +1626,7 @@
(match_operand:SI 1 "general_src_operand" "roJS,i")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
{
/* Must clear condition codes, since the move.l bases them on
the entire 32 bits, not just the desired 8 bits. */
@@ -1893,7 +1893,7 @@
operands[1] = operands[2];
operands[2] = tmp;
}
- if (GET_CODE (operands[1]) == REG
+ if (REG_P (operands[1])
&& REGNO (operands[1]) == REGNO (operands[3]))
output_asm_insn ("add%.l %2,%3", operands);
else
@@ -2271,7 +2271,7 @@
if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
return
"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0";
- if (GET_CODE (operands[1]) == REG)
+ if (REG_P (operands[1]))
operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
|| GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
@@ -2318,7 +2318,7 @@
"!TARGET_COLDFIRE"
{
CC_STATUS_INIT;
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[2] = adjust_address (operands[0], SImode, 4);
@@ -2347,7 +2347,7 @@
""
{
CC_STATUS_INIT;
- if (GET_CODE (operands[1]) == REG)
+ if (REG_P (operands[1]))
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
operands[1] = adjust_address (operands[1], SImode, 4);
@@ -2374,7 +2374,7 @@
rtx high, low;
rtx xoperands[2];
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
{
low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
high = operands[2];
@@ -2844,7 +2844,7 @@
""
{
CC_STATUS_INIT;
- if (GET_CODE (operands[1]) == REG)
+ if (REG_P (operands[1]))
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
operands[1] = adjust_address (operands[1], SImode, 4);
@@ -2873,7 +2873,7 @@
rtx high, low;
rtx xoperands[2];
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
{
low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
high = operands[2];
@@ -3717,7 +3717,7 @@
int byte_mode;
CC_STATUS_INIT;
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[0] = adjust_address (operands[0], SImode, 4);
@@ -3811,9 +3811,9 @@
""
{
CC_STATUS_INIT;
- if (GET_CODE (operands[2]) != REG)
+ if (!REG_P (operands[2]))
operands[2] = adjust_address (operands[2], HImode, 2);
- if (GET_CODE (operands[2]) != REG
+ if (!REG_P (operands[2])
|| REGNO (operands[2]) != REGNO (operands[0]))
output_asm_insn ("move%.w %2,%0", operands);
return "swap %0\;mov%.w %1,%0";
@@ -3929,7 +3929,7 @@
{
if (which_alternative == 0)
return "neg%.l %0\;negx%.l %0";
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[1] = adjust_address (operands[0], SImode, 4);
@@ -4672,7 +4672,7 @@
(const_int 32)) 6))]
""
{
- if (GET_CODE (operands[1]) != REG)
+ if (!REG_P (operands[1]))
operands[1] = adjust_address (operands[1], HImode, 2);
return "move%.w %1,%0";
}
@@ -4912,7 +4912,7 @@
;; (const_int 32)))]
;; ""
;;{
-;; if (GET_CODE (operands[1]) == REG)
+;; if (REG_P (operands[1]))
;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
;; else
;; operands[2] = adjust_address (operands[1], SImode, 4);
@@ -5746,7 +5746,7 @@
if (operands[1] == const1_rtx
&& CONST_INT_P (operands[2]))
{
- int width = GET_CODE (operands[0]) == REG ? 31 : 7;
+ int width = REG_P (operands[0]) ? 31 : 7;
return output_btst (operands,
GEN_INT (width - INTVAL (operands[2])),
operands[0], insn, 1000);
@@ -5773,7 +5773,7 @@
if (operands[1] == const1_rtx
&& CONST_INT_P (operands[2]))
{
- int width = GET_CODE (operands[0]) == REG ? 31 : 7;
+ int width = REG_P (operands[0]) ? 31 : 7;
return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
operands[0], insn, 1000);
/* Pass 1000 as SIGNPOS argument so that btst will
@@ -6049,7 +6049,7 @@
cc_status = cc_prev_status;
return "jeq %l1";
}
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[3] = adjust_address (operands[0], SImode, 4);
@@ -6092,7 +6092,7 @@
return "jne %l1";
}
CC_STATUS_INIT;
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[3] = adjust_address (operands[0], SImode, 4);
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 21d15e0a6bb..d4f417a16e9 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -343,7 +343,7 @@ mcore_print_operand_address (FILE * stream, machine_mode /*mode*/, rtx x)
rtx base = XEXP (x, 0);
rtx index = XEXP (x, 1);
- if (GET_CODE (base) != REG)
+ if (!REG_P (base))
{
/* Ensure that BASE is a register (one of them must be). */
rtx temp = base;
@@ -1282,9 +1282,9 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
rtx dst = operands[0];
rtx src = operands[1];
- if (GET_CODE (dst) == REG)
+ if (REG_P (dst))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
if (REGNO (src) == CC_REG) /* r-c */
return "mvc\t%0";
@@ -1352,9 +1352,9 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
rtx dst = operands[0];
rtx src = operands[1];
- if (GET_CODE (dst) == REG)
+ if (REG_P (dst))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int dstreg = REGNO (dst);
int srcreg = REGNO (src);
@@ -1373,13 +1373,13 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
if (GET_CODE (memexp) == LABEL_REF)
return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
- else if (GET_CODE (memexp) == REG)
+ else if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -1437,7 +1437,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
else
gcc_unreachable ();
}
- else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
+ else if (GET_CODE (dst) == MEM && REG_P (src))
return "stw\t%1,%0\n\tstw\t%R1,%R0";
else
gcc_unreachable ();
@@ -2291,25 +2291,25 @@ is_cond_candidate (rtx insn)
dst = XEXP (pat, 0);
- if ((GET_CODE (dst) != REG &&
+ if ((!REG_P (dst) &&
GET_CODE (dst) != SUBREG) ||
GET_MODE (dst) != SImode)
return COND_NO;
src = XEXP (pat, 1);
- if ((GET_CODE (src) == REG ||
+ if ((REG_P (src) ||
(GET_CODE (src) == SUBREG &&
- GET_CODE (SUBREG_REG (src)) == REG)) &&
+ REG_P (SUBREG_REG (src)))) &&
GET_MODE (src) == SImode)
return COND_MOV_INSN;
else if (CONST_INT_P (src) &&
INTVAL (src) == 0)
return COND_CLR_INSN;
else if (GET_CODE (src) == PLUS &&
- (GET_CODE (XEXP (src, 0)) == REG ||
+ (REG_P (XEXP (src, 0)) ||
(GET_CODE (XEXP (src, 0)) == SUBREG &&
- GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
+ REG_P (SUBREG_REG (XEXP (src, 0))))) &&
GET_MODE (XEXP (src, 0)) == SImode &&
CONST_INT_P (XEXP (src, 1)) &&
INTVAL (XEXP (src, 1)) == 1)
@@ -2320,9 +2320,9 @@ is_cond_candidate (rtx insn)
(GET_CODE (src) == PLUS &&
CONST_INT_P (XEXP (src, 1)) &&
INTVAL (XEXP (src, 1)) == -1)) &&
- (GET_CODE (XEXP (src, 0)) == REG ||
+ (REG_P (XEXP (src, 0)) ||
(GET_CODE (XEXP (src, 0)) == SUBREG &&
- GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
+ REG_P (SUBREG_REG (XEXP (src, 0))))) &&
GET_MODE (XEXP (src, 0)) == SImode)
return COND_DEC_INSN;
@@ -2690,7 +2690,7 @@ mcore_is_same_reg (rtx x, rtx y)
while (GET_CODE (y) == SUBREG)
y = SUBREG_REG (y);
- if (GET_CODE(x) == REG && GET_CODE(y) == REG && REGNO(x) == REGNO(y))
+ if (REG_P (x) && REG_P (y) && REGNO(x) == REGNO(y))
return 1;
return 0;
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index 71f0bc0b17c..755a322139c 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -674,7 +674,7 @@
that we can later fold in the fp/sp offset from frame pointer
elimination. */
if (flag_omit_frame_pointer
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& (REGNO (operands[1]) == VIRTUAL_STACK_VARS_REGNUM
|| REGNO (operands[1]) == FRAME_POINTER_REGNUM))
{
@@ -1367,7 +1367,7 @@
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != MEM
|| XEXP (operands[1], 0) != stack_pointer_rtx
- || GET_CODE (operands[0]) != REG
+ || !REG_P (operands[0])
|| REGNO (operands[0]) + INTVAL (operands[2]) != 16)
FAIL;
@@ -1387,7 +1387,7 @@
[(match_parallel 0 "mcore_load_multiple_operation"
[(set (match_operand:SI 1 "mcore_arith_reg_operand" "=r")
(mem:SI (match_operand:SI 2 "register_operand" "r")))])]
- "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
+ "REG_P (operands[2]) && REGNO (operands[2]) == STACK_POINTER_REGNUM"
"ldm %1-r15,(%2)")
(define_expand "store_multiple"
@@ -1405,7 +1405,7 @@
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[0]) != MEM
|| XEXP (operands[0], 0) != stack_pointer_rtx
- || GET_CODE (operands[1]) != REG
+ || !REG_P (operands[1])
|| REGNO (operands[1]) + INTVAL (operands[2]) != 16)
FAIL;
@@ -1426,7 +1426,7 @@
[(match_parallel 0 "mcore_store_multiple_operation"
[(set (mem:SI (match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 1 "mcore_arith_reg_operand" "r"))])]
- "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
+ "REG_P (operands[2]) && REGNO (operands[2]) == STACK_POINTER_REGNUM"
"stm %1-r15,(%2)")
;; ------------------------------------------------------------------------
@@ -2764,7 +2764,7 @@
(mcore_byte_offset (INTVAL (operands[3])) > -1 ||
mcore_halfword_offset (INTVAL (operands[3])) > -1) &&
! MEM_VOLATILE_P (operands[4]) &&
- GET_CODE (XEXP (operands[4], 0)) == REG"
+ REG_P (XEXP (operands[4], 0))"
"*
{
int ofs;
@@ -2839,12 +2839,12 @@
{
unsigned int op0 = REGNO (operands[0]);
- if (GET_CODE (operands[3]) == REG)
+ if (REG_P (operands[3]))
{
if (REGNO (operands[3]) == op0 && CONST_INT_P (operands[4])
&& INTVAL (operands[4]) == 0)
return \"btsti %1,%2\\n\\tclrf %0\";
- else if (GET_CODE (operands[4]) == REG)
+ else if (REG_P (operands[4]))
{
if (REGNO (operands[4]) == op0)
return \"btsti %1,%2\\n\\tmovf %0,%3\";
@@ -2856,7 +2856,7 @@
}
else if (CONST_INT_P (operands[3])
&& INTVAL (operands[3]) == 0
- && GET_CODE (operands[4]) == REG)
+ && REG_P (operands[4]))
return \"btsti %1,%2\\n\\tclrt %0\";
gcc_unreachable ();
diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md
index 344a1e0b14e..c29792cc520 100644
--- a/gcc/config/mcore/predicates.md
+++ b/gcc/config/mcore/predicates.md
@@ -28,7 +28,7 @@
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
return REGNO (op) != CC_REG;
return 1;
@@ -51,7 +51,7 @@
(define_predicate "mcore_general_movdst_operand"
(match_code "mem,reg,subreg")
{
- if (GET_CODE (op) == REG && REGNO (op) == CC_REG)
+ if (REG_P (op) && REGNO (op) == CC_REG)
return 0;
return general_operand (op, mode);
@@ -262,7 +262,7 @@
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+ || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
return 0;
@@ -274,7 +274,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != SImode
|| REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
|| GET_CODE (SET_SRC (elt)) != MEM
@@ -303,7 +303,7 @@
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+ || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return 0;
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -314,7 +314,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
+ || !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != SImode
|| REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
|| GET_CODE (SET_DEST (elt)) != MEM
diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
index 5e1d79a2444..831e888a180 100644
--- a/gcc/config/microblaze/constraints.md
+++ b/gcc/config/microblaze/constraints.md
@@ -74,4 +74,4 @@
(define_memory_constraint "Q"
"Memory operand which is a single register."
(and (match_code "mem")
- (match_test "GET_CODE ( XEXP (op, 0)) == REG")))
+ (match_test "REG_P ( XEXP (op, 0))")))
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index 529d54cefc4..f9c2adf9ab7 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -311,19 +311,19 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
plus0 = XEXP (addr, 0);
plus1 = XEXP (addr, 1);
- if (GET_CODE (plus0) != REG)
+ if (!REG_P (plus0))
return 0;
- if (GET_CODE (plus0) == REG && CONST_INT_P (plus1)
+ if (REG_P (plus0) && CONST_INT_P (plus1)
&& SMALL_INT (plus1))
{
return 1;
}
- else if (GET_CODE (plus1) == REG && CONST_INT_P (plus0))
+ else if (REG_P (plus1) && CONST_INT_P (plus0))
{
return 1;
}
- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
+ else if (REG_P (plus0) && REG_P (plus1))
{
return 1;
}
@@ -356,7 +356,7 @@ double_memory_operand (rtx op, machine_mode mode)
register from memory, when we could just reload directly from
memory. */
if (reload_in_progress
- && GET_CODE (op) == REG
+ && REG_P (op)
&& REGNO (op) >= FIRST_PSEUDO_REGISTER
&& reg_renumber[REGNO (op)] < 0
&& reg_equiv_mem (REGNO (op)) != 0
@@ -409,7 +409,7 @@ microblaze_valid_base_register_p (rtx x,
if (!strict && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
- return (GET_CODE (x) == REG
+ return (REG_P (x)
&& microblaze_regno_ok_for_base_p (REGNO (x), strict));
}
@@ -674,7 +674,7 @@ microblaze_valid_index_register_p (rtx x,
if (!strict && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
- return (GET_CODE (x) == REG
+ return (REG_P (x)
/* A base register is good enough to be an index register on MicroBlaze. */
&& microblaze_regno_ok_for_base_p (REGNO (x), strict));
}
@@ -841,7 +841,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
return false;
}
- else if (GET_CODE (xplus1) == REG
+ else if (REG_P (xplus1)
&& microblaze_valid_index_register_p (xplus1, mode,
strict)
&& (GET_MODE_SIZE (mode) <= UNITS_PER_WORD))
@@ -2437,7 +2437,7 @@ print_operand (FILE * file, rtx op, int letter)
else if (letter == 'y')
{
rtx mem_reg = XEXP (op, 0);
- if (GET_CODE (mem_reg) == REG)
+ if (REG_P (mem_reg))
{
register int regnum = REGNO (mem_reg);
fprintf (file, "%s", reg_names[regnum]);
@@ -2522,14 +2522,14 @@ print_operand (FILE * file, rtx op, int letter)
fputs (code == EQ ? "t" : "f", file);
else if (code == CONST
- && ((GET_CODE (XEXP (op, 0)) == REG)
+ && ((REG_P (XEXP (op, 0)))
|| (GET_CODE (XEXP (op, 0)) == UNSPEC)))
{
print_operand (file, XEXP (op, 0), letter);
}
else if (code == CONST
&& (GET_CODE (XEXP (op, 0)) == PLUS)
- && (GET_CODE (XEXP (XEXP (op, 0), 0)) == REG)
+ && (REG_P (XEXP (XEXP (op, 0), 0)))
&& (GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST))
{
print_operand_address (file, XEXP (op, 0));
@@ -3411,7 +3411,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
result = expand_pic_symbol_ref (mode, op1);
- if (TARGET_PIC_DATA_TEXT_REL && GET_CODE (op0) == REG
+ if (TARGET_PIC_DATA_TEXT_REL && REG_P (op0)
&& REGNO (op0) >= FIRST_PSEUDO_REGISTER)
result = force_reg (SImode, result);
@@ -3472,7 +3472,7 @@ int
microblaze_expand_shift (rtx operands[])
{
gcc_assert ((CONST_INT_P (operands[2]))
- || (GET_CODE (operands[2]) == REG)
+ || (REG_P (operands[2]))
|| (GET_CODE (operands[2]) == SUBREG));
/* Shift by one -- generate pattern. */
@@ -3483,9 +3483,9 @@ microblaze_expand_shift (rtx operands[])
if (TARGET_BARREL_SHIFT)
return 0;
- gcc_assert ((GET_CODE (operands[0]) == REG)
+ gcc_assert ((REG_P (operands[0]))
|| (GET_CODE (operands[0]) == SUBREG)
- || (GET_CODE (operands[1]) == REG)
+ || (REG_P (operands[1]))
|| (GET_CODE (operands[1]) == SUBREG));
/* Shift by zero -- copy regs if necessary. */
@@ -3594,7 +3594,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
rtx comp_reg = gen_reg_rtx (SImode);
rtx condition;
- gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
+ gcc_assert ((REG_P (cmp_op0)) || (GET_CODE (cmp_op0) == SUBREG));
/* If comparing against zero, just test source reg. */
if (cmp_op1 == const0_rtx)
@@ -3630,7 +3630,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
rtx comp_reg = gen_reg_rtx (SImode);
rtx condition;
- gcc_assert ((GET_CODE (cmp_op0) == REG)
+ gcc_assert ((REG_P (cmp_op0))
|| (GET_CODE (cmp_op0) == SUBREG));
/* If comparing against zero, just test source reg. */
diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
index fa0806e0fd9..5dea2d6f201 100644
--- a/gcc/config/microblaze/microblaze.h
+++ b/gcc/config/microblaze/microblaze.h
@@ -372,7 +372,7 @@ extern enum reg_class microblaze_regno_to_class[];
since they may change into reg + const, which the patterns
can't handle yet. */
#define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \
- || (GET_CODE (X) == REG && X != arg_pointer_rtx\
+ || (REG_P (X) && X != arg_pointer_rtx\
&& ! (REGNO (X) >= FIRST_PSEUDO_REGISTER \
&& REGNO (X) <= LAST_VIRTUAL_REGISTER)))
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 39e447ba58f..a4ffb50797f 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -751,8 +751,8 @@
[(set (match_operand:DI 0 "register_operand" "")
(not:DI (match_operand:DI 1 "register_operand" "")))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))"
[(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
(set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
@@ -966,8 +966,8 @@
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))
&& (REGNO(operands[0]) == (REGNO(operands[1]) + 1))"
[(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
@@ -978,8 +978,8 @@
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))
&& (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
[(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
@@ -1277,8 +1277,8 @@
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))
&& (REGNO (operands[0]) == (REGNO (operands[1]) + 1))"
[(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
@@ -1288,8 +1288,8 @@
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))
&& (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
[(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
@@ -1810,7 +1810,7 @@
(label_ref (match_operand 0 "" "")))]
""
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
return "br%?\t%0";
else
return "bri%?\t%l0";
@@ -1824,7 +1824,7 @@
""
{
rtx dest = operands[0];
- if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
+ if (!REG_P (dest) || GET_MODE (dest) != Pmode)
operands[0] = copy_to_mode_reg (Pmode, dest);
emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
@@ -2063,7 +2063,7 @@
XEXP (operands[0], 0) = temp;
}
- if ((GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
+ if ((!REG_P (addr) && !CONSTANT_ADDRESS_P (addr))
|| !call_insn_operand (addr, VOIDmode))
XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
@@ -2136,7 +2136,7 @@
}
} else if (CONST_INT_P (target))
return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
- else if (GET_CODE (target) == REG)
+ else if (REG_P (target))
return "brald\tr15,%0\;%#";
else {
fprintf (stderr,"Unsupported call insn\n");
@@ -2167,7 +2167,7 @@
XEXP (operands[1], 0) = temp;
}
- if ((GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
+ if ((!REG_P (addr) && !CONSTANT_ADDRESS_P (addr))
|| !call_insn_operand (addr, VOIDmode))
XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
@@ -2251,7 +2251,7 @@
}
else if (CONST_INT_P (target))
return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
- else if (GET_CODE (target) == REG)
+ else if (REG_P (target))
return "brald\tr15,%1\;%#";
else
return "Unsupported call insn\n";
diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md
index 7ee237c556b..10ec60ca70c 100644
--- a/gcc/config/microblaze/predicates.md
+++ b/gcc/config/microblaze/predicates.md
@@ -101,14 +101,14 @@
(define_predicate "call_insn_simple_operand"
(and (match_test "CALL_INSN_OP (op)")
- (match_test "GET_CODE (op) == REG || GET_CODE (op) == SYMBOL_REF || CONST_INT_P (op)")))
+ (match_test "REG_P (op) || GET_CODE (op) == SYMBOL_REF || CONST_INT_P (op)")))
;; Return if OPERAND is valid as a source operand for a move instruction.
(define_predicate "move_src_operand"
(and (
not (
and (match_code "plus")
- (not (match_test "(GET_CODE (XEXP (op, 0)) == REG) ^ (GET_CODE (XEXP (op,1)) == REG)"))
+ (not (match_test "(REG_P (XEXP (op, 0))) ^ (REG_P (XEXP (op,1)))"))
)
)
(match_operand 0 "general_operand"))
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 96dff88c77d..e72e0d57a97 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -17087,7 +17087,7 @@ mips_expand_builtin_msa_test_branch (enum insn_code icode, tree exp)
create_fixed_operand (&ops[2], const0_rtx);
/* Make sure that the operand 1 is a REG. */
- if (GET_CODE (ops[1].value) != REG)
+ if (!REG_P (ops[1].value))
ops[1].value = force_reg (ops[1].mode, ops[1].value);
if ((cbranch = maybe_gen_insn (icode, 3, ops)) == NULL_RTX)
diff --git a/gcc/config/mn10300/predicates.md b/gcc/config/mn10300/predicates.md
index 6078d3cf11e..210d7140111 100644
--- a/gcc/config/mn10300/predicates.md
+++ b/gcc/config/mn10300/predicates.md
@@ -31,9 +31,9 @@
(match_code "symbol_ref,reg,unspec")
{
if (flag_pic)
- return (satisfies_constraint_S (op) || GET_CODE (op) == REG);
+ return (satisfies_constraint_S (op) || REG_P (op));
- return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op));
})
(define_predicate "impossible_plus_operand"
diff --git a/gcc/config/moxie/moxie.md b/gcc/config/moxie/moxie.md
index fa750d45401..eb2250fc260 100644
--- a/gcc/config/moxie/moxie.md
+++ b/gcc/config/moxie/moxie.md
@@ -382,9 +382,9 @@
""
"
/* Force the compare operands into registers. */
- if (GET_CODE (operands[1]) != REG)
+ if (!REG_P (operands[1]))
operands[1] = force_reg (SImode, operands[1]);
- if (GET_CODE (operands[2]) != REG)
+ if (!REG_P (operands[2]))
operands[2] = force_reg (SImode, operands[2]);
")
diff --git a/gcc/config/moxie/predicates.md b/gcc/config/moxie/predicates.md
index b7deba669ca..c61ce12ac28 100644
--- a/gcc/config/moxie/predicates.md
+++ b/gcc/config/moxie/predicates.md
@@ -33,7 +33,7 @@
if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (op, 0), 0))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1))
&& IN_RANGE (INTVAL (XEXP (XEXP (op, 0), 1)), -32768, 32767))
return 1;
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index c7f04a0bfa5..d28023b339f 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -3167,7 +3167,7 @@ msp430_fixup_compare_operands (machine_mode my_mode, rtx * operands)
if (msp430_reversible_cmp_operator (operands[0], VOIDmode))
const_op_idx = 2;
- if (GET_CODE (operands[const_op_idx]) != REG
+ if (!REG_P (operands[const_op_idx])
&& GET_CODE (operands[const_op_idx]) != MEM)
operands[const_op_idx] = copy_to_mode_reg (my_mode, operands[const_op_idx]);
}
diff --git a/gcc/config/nds32/nds32-fp-as-gp.c b/gcc/config/nds32/nds32-fp-as-gp.c
index 278df99bc74..b8b038aaa7a 100644
--- a/gcc/config/nds32/nds32-fp-as-gp.c
+++ b/gcc/config/nds32/nds32-fp-as-gp.c
@@ -75,7 +75,7 @@ nds32_get_symbol_count (void)
rtx pattern = PATTERN (insn);
rtx mem;
gcc_assert (GET_CODE (pattern) == SET);
- if (GET_CODE (SET_SRC (pattern)) == REG )
+ if (REG_P (SET_SRC (pattern)) )
mem = SET_DEST (pattern);
else
mem = SET_SRC (pattern);
diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c
index 3e6371730d0..1bc365f11ba 100644
--- a/gcc/config/nds32/nds32-md-auxiliary.c
+++ b/gcc/config/nds32/nds32-md-auxiliary.c
@@ -1486,12 +1486,12 @@ nds32_mem_format (rtx op)
op = XEXP (op, 0);
/* 45 format. */
- if (GET_CODE (op) == REG
+ if (REG_P (op)
&& ((mode_test == SImode) || (mode_test == SFmode)))
return ADDRESS_REG;
/* 333 format for QI/HImode. */
- if (GET_CODE (op) == REG && (REGNO (op) < R8_REGNUM))
+ if (REG_P (op) && (REGNO (op) < R8_REGNUM))
return ADDRESS_LO_REG_IMM3U;
/* post_inc 333 format. */
@@ -1517,7 +1517,7 @@ nds32_mem_format (rtx op)
}
if ((GET_CODE (op) == PLUS)
- && (GET_CODE (XEXP (op, 0)) == REG)
+ && (REG_P (XEXP (op, 0)))
&& (CONST_INT_P (XEXP (op, 1))))
{
val = INTVAL (XEXP (op, 1));
diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md
index 96810fabecd..7a767e7e426 100644
--- a/gcc/config/nds32/nds32-multiple.md
+++ b/gcc/config/nds32/nds32-multiple.md
@@ -59,7 +59,7 @@
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
- || GET_CODE (operands[0]) != REG
+ || !REG_P (operands[0])
|| GET_CODE (operands[1]) != MEM
|| MEM_VOLATILE_P (operands[1])
|| REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM)
@@ -1909,7 +1909,7 @@
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[0]) != MEM
- || GET_CODE (operands[1]) != REG
+ || !REG_P (operands[1])
|| MEM_VOLATILE_P (operands[0])
|| REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
FAIL;
diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c
index d99a70a2b62..649b34d3c5b 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -73,7 +73,7 @@ nds32_consecutive_registers_load_store_p (rtx op,
elt_mem = load_p ? SET_SRC (elt) : SET_DEST (elt);
/* If elt_reg is not a expected reg rtx, return false. */
- if (GET_CODE (elt_reg) != REG || GET_MODE (elt_reg) != SImode)
+ if (!REG_P (elt_reg) || GET_MODE (elt_reg) != SImode)
return false;
/* If elt_mem is not a expected mem rtx, return false. */
if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
@@ -135,7 +135,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
Note that the form is different between load and store operation. */
if (load_p)
{
- if (GET_CODE (SET_DEST (elt)) != REG
+ if (!REG_P (SET_DEST (elt))
|| GET_CODE (SET_SRC (elt)) != MEM)
return false;
@@ -143,7 +143,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
}
else
{
- if (GET_CODE (SET_SRC (elt)) != REG
+ if (!REG_P (SET_SRC (elt))
|| GET_CODE (SET_DEST (elt)) != MEM)
return false;
@@ -303,7 +303,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
index++;
if (GET_CODE (elt_mem) != MEM
- || GET_CODE (elt_reg) != REG
+ || !REG_P (elt_reg)
|| REGNO (elt_reg) != FP_REGNUM)
return false;
}
@@ -315,7 +315,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
index++;
if (GET_CODE (elt_mem) != MEM
- || GET_CODE (elt_reg) != REG
+ || !REG_P (elt_reg)
|| REGNO (elt_reg) != GP_REGNUM)
return false;
}
@@ -327,7 +327,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
index++;
if (GET_CODE (elt_mem) != MEM
- || GET_CODE (elt_reg) != REG
+ || !REG_P (elt_reg)
|| REGNO (elt_reg) != LP_REGNUM)
return false;
}
@@ -346,7 +346,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
elt_plus = SET_SRC (elt);
/* Check this is (set (stack_reg) (plus stack_reg const)) pattern. */
- if (GET_CODE (elt_reg) != REG
+ if (!REG_P (elt_reg)
|| GET_CODE (elt_plus) != PLUS
|| REGNO (elt_reg) != SP_REGNUM)
return false;
diff --git a/gcc/config/nds32/nds32-relax-opt.c b/gcc/config/nds32/nds32-relax-opt.c
index 5da27530cd6..873dc5260ec 100644
--- a/gcc/config/nds32/nds32-relax-opt.c
+++ b/gcc/config/nds32/nds32-relax-opt.c
@@ -110,7 +110,7 @@ nds32_reg_base_load_store_p (rtx_insn *insn)
|| (GET_CODE (mem_src) == SIGN_EXTEND))
mem_src = XEXP (mem_src, 0);
- if (GET_CODE (XEXP (mem_src, 0)) == REG)
+ if (REG_P (XEXP (mem_src, 0)))
return true;
}
@@ -185,7 +185,7 @@ nds32_plus_reg_load_store_p (rtx_insn *insn)
else
return false;
- if (GET_CODE (XEXP (mem_src, 0)) == REG)
+ if (REG_P (XEXP (mem_src, 0)))
return true;
}
diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c
index 5b1dfedf30d..44d2ad83e9f 100644
--- a/gcc/config/nds32/nds32.c
+++ b/gcc/config/nds32/nds32.c
@@ -1440,7 +1440,7 @@ nds32_address_register_rtx_p (rtx x, bool strict)
{
int regno;
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
return false;
regno = REGNO (x);
@@ -2575,7 +2575,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
if (GET_CODE (x) == POST_MODIFY
&& mode == DFmode)
{
- if (GET_CODE (XEXP (x, 0)) == REG
+ if (REG_P (XEXP (x, 0))
&& GET_CODE (XEXP (x, 1)) == PLUS)
{
rtx plus_op = XEXP (x, 1);
@@ -2629,7 +2629,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
}
/* Now check [reg], [symbol_ref], and [const]. */
- if (GET_CODE (x) != REG
+ if (!REG_P (x)
&& GET_CODE (x) != SYMBOL_REF
&& GET_CODE (x) != CONST)
return false;
@@ -2719,7 +2719,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
=> [Ra], Rb */
/* (mem (post_modify (reg) (plus (reg) (const_int))))
=> [Ra], const_int */
- if (GET_CODE (XEXP (x, 0)) == REG
+ if (REG_P (XEXP (x, 0))
&& GET_CODE (XEXP (x, 1)) == PLUS)
{
rtx plus_op = XEXP (x, 1);
diff --git a/gcc/config/nios2/predicates.md b/gcc/config/nios2/predicates.md
index a1c4ca795d7..4ad337ddde3 100644
--- a/gcc/config/nios2/predicates.md
+++ b/gcc/config/nios2/predicates.md
@@ -157,5 +157,5 @@
(match_code "mem")
{
/* ldex/ldsex/stex/stsex cannot handle memory addresses with offsets. */
- return GET_CODE (XEXP (op, 0)) == REG;
+ return REG_P (XEXP (op, 0));
})
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index ff5bfedd06d..6795fc393fd 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1101,7 +1101,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
/* Special case. Get the SYMBOL_REF into a register and use indexing.
That should always be safe. */
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
{
rtx reg = force_reg (Pmode, XEXP (x, 1));
@@ -1114,7 +1114,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& CONST_INT_P (XEXP (x, 1))
&& ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
&& !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
- || GET_CODE (XEXP (x, 0)) == REG))
+ || REG_P (XEXP (x, 0))))
{
rtx int_part, ptr_reg;
int newoffset;
@@ -1180,11 +1180,11 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
rtx reg1, reg2;
reg1 = XEXP (x, 1);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
reg2 = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
reg2 = force_reg (Pmode, force_operand (reg2, 0));
return force_reg (Pmode,
@@ -1221,15 +1221,15 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
/* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
then pa_emit_move_sequence will turn on REG_POINTER so we'll know
it's a base register below. */
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
reg2 = force_reg (Pmode, force_operand (reg2, 0));
/* Figure out what the base and index are. */
- if (GET_CODE (reg1) == REG
+ if (REG_P (reg1)
&& REG_POINTER (reg1))
{
base = reg1;
@@ -1239,7 +1239,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
GEN_INT (shift_val)),
XEXP (x, 1));
}
- else if (GET_CODE (reg2) == REG
+ else if (REG_P (reg2)
&& REG_POINTER (reg2))
{
base = reg2;
@@ -1261,7 +1261,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
val /= (1 << shift_val);
reg1 = XEXP (XEXP (idx, 0), 0);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
@@ -1300,12 +1300,12 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
/* First get A into a register. */
reg1 = XEXP (XEXP (idx, 0), 0);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
/* And get B into a register. */
reg2 = XEXP (idx, 1);
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
reg2 = force_reg (Pmode, force_operand (reg2, 0));
reg1 = force_reg (Pmode,
@@ -1371,11 +1371,11 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
rtx reg1, reg2;
reg1 = XEXP (x, 1);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
reg2 = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
reg2 = force_reg (Pmode, force_operand (reg2, 0));
return
@@ -1403,7 +1403,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
= force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
/ INTVAL (XEXP (XEXP (x, 0), 1))));
regx2 = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (regx2) != REG)
+ if (!REG_P (regx2))
regx2 = force_reg (Pmode, force_operand (regx2, 0));
regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
regx2, regx1));
@@ -1666,12 +1666,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
if (scratch_reg
- && reload_in_progress && GET_CODE (operand0) == REG
+ && reload_in_progress && REG_P (operand0)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
operand0 = reg_equiv_mem (REGNO (operand0));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand0) == SUBREG
- && GET_CODE (SUBREG_REG (operand0)) == REG
+ && REG_P (SUBREG_REG (operand0))
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
@@ -1683,12 +1683,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
}
if (scratch_reg
- && reload_in_progress && GET_CODE (operand1) == REG
+ && reload_in_progress && REG_P (operand1)
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
operand1 = reg_equiv_mem (REGNO (operand1));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand1) == SUBREG
- && GET_CODE (SUBREG_REG (operand1)) == REG
+ && REG_P (SUBREG_REG (operand1))
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
@@ -1852,7 +1852,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
/* Handle secondary reloads for SAR. These occur when trying to load
the SAR from memory or a constant. */
else if (scratch_reg
- && GET_CODE (operand0) == REG
+ && REG_P (operand0)
&& REGNO (operand0) < FIRST_PSEUDO_REGISTER
&& REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
&& (GET_CODE (operand1) == MEM || CONST_INT_P (operand1)))
@@ -2137,7 +2137,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
safe to be used as the base in an indexed address.
Don't mark hard registers though. That loses. */
- if (GET_CODE (operand0) == REG
+ if (REG_P (operand0)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
mark_reg_pointer (operand0, BITS_PER_UNIT);
if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
@@ -2568,8 +2568,8 @@ pa_output_move_double (rtx *operands)
rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
operands[0] = XEXP (addr, 0);
- gcc_assert (GET_CODE (operands[1]) == REG
- && GET_CODE (operands[0]) == REG);
+ gcc_assert (REG_P (operands[1])
+ && REG_P (operands[0]));
gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
@@ -2585,8 +2585,8 @@ pa_output_move_double (rtx *operands)
rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
operands[0] = XEXP (addr, 0);
- gcc_assert (GET_CODE (operands[1]) == REG
- && GET_CODE (operands[0]) == REG);
+ gcc_assert (REG_P (operands[1])
+ && REG_P (operands[0]));
gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
/* No overlap between high target register and address
@@ -2608,8 +2608,8 @@ pa_output_move_double (rtx *operands)
rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
operands[1] = XEXP (addr, 0);
- gcc_assert (GET_CODE (operands[0]) == REG
- && GET_CODE (operands[1]) == REG);
+ gcc_assert (REG_P (operands[0])
+ && REG_P (operands[1]));
if (!reg_overlap_mentioned_p (high_reg, addr))
{
@@ -2635,8 +2635,8 @@ pa_output_move_double (rtx *operands)
rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
operands[1] = XEXP (addr, 0);
- gcc_assert (GET_CODE (operands[0]) == REG
- && GET_CODE (operands[1]) == REG);
+ gcc_assert (REG_P (operands[0])
+ && REG_P (operands[1]));
if (!reg_overlap_mentioned_p (high_reg, addr))
{
@@ -2815,7 +2815,7 @@ pa_output_fp_move_double (rtx *operands)
arbitrary address here including pre/post increment/decrement.
so avoid this in the MD. */
- gcc_assert (GET_CODE (operands[0]) == REG);
+ gcc_assert (REG_P (operands[0]));
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
xoperands[0] = operands[0];
@@ -2832,9 +2832,9 @@ find_addr_reg (rtx addr)
{
while (GET_CODE (addr) == PLUS)
{
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
addr = XEXP (addr, 0);
- else if (GET_CODE (XEXP (addr, 1)) == REG)
+ else if (REG_P (XEXP (addr, 1)))
addr = XEXP (addr, 1);
else if (CONSTANT_P (XEXP (addr, 0)))
addr = XEXP (addr, 1);
@@ -2843,7 +2843,7 @@ find_addr_reg (rtx addr)
else
gcc_unreachable ();
}
- gcc_assert (GET_CODE (addr) == REG);
+ gcc_assert (REG_P (addr));
return addr;
}
@@ -3458,7 +3458,7 @@ remove_useless_addtr_insns (int check_notes)
/* If the destination is CCFP, then we've found an fcmp insn. */
tmp = SET_DEST (tmp);
- if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
+ if (REG_P (tmp) && REGNO (tmp) == 0)
{
fcmp_count++;
continue;
@@ -3470,7 +3470,7 @@ remove_useless_addtr_insns (int check_notes)
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
&& GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
- && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
+ && REG_P (XEXP (XEXP (SET_SRC (tmp), 0), 0))
&& REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
{
fbranch_count++;
@@ -3498,7 +3498,7 @@ remove_useless_addtr_insns (int check_notes)
/* The destination must be CCFP, which is register zero. */
tmp = SET_DEST (tmp);
- if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
+ if (!REG_P (tmp) || REGNO (tmp) != 0)
continue;
/* INSN should be a set of CCFP.
@@ -3516,7 +3516,7 @@ remove_useless_addtr_insns (int check_notes)
/* As does another fcmp insn. */
if (NONJUMP_INSN_P (next)
&& GET_CODE (PATTERN (next)) == SET
- && GET_CODE (SET_DEST (PATTERN (next))) == REG
+ && REG_P (SET_DEST (PATTERN (next)))
&& REGNO (SET_DEST (PATTERN (next))) == 0)
break;
@@ -3535,7 +3535,7 @@ remove_useless_addtr_insns (int check_notes)
&& SET_DEST (pattern) == pc_rtx
&& GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
&& GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
- && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
+ && REG_P (XEXP (XEXP (SET_SRC (pattern), 0), 0))
&& REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
&& GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
&& (fcmp_count == fbranch_count
@@ -5087,7 +5087,7 @@ pa_adjust_insn_length (rtx_insn *insn, int length)
general register register. */
else if (GET_CODE (pat) == PARALLEL
&& GET_CODE (XVECEXP (pat, 0, 1)) == SET
- && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
+ && REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
&& ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
&& length == 4
&& ! forward_branch_p (insn))
@@ -5371,8 +5371,8 @@ pa_print_operand (FILE *file, rtx x, int code)
fputs (",ma", file);
break;
case PLUS:
- if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
+ if (REG_P (XEXP (XEXP (x, 0), 0))
+ && REG_P (XEXP (XEXP (x, 0), 1)))
{
if (ASSEMBLER_DIALECT == 0)
fputs ("x", file);
@@ -5424,7 +5424,7 @@ pa_print_operand (FILE *file, rtx x, int code)
default:
gcc_unreachable ();
}
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
fputs (reg_names [REGNO (x)], file);
if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
@@ -5462,8 +5462,8 @@ pa_print_operand (FILE *file, rtx x, int code)
fprintf (file, "%s(%s)",
reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
- else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
+ else if (REG_P (XEXP (XEXP (x, 0), 0))
+ && REG_P (XEXP (XEXP (x, 0), 1)))
{
/* Because the REG_POINTER flag can get lost during reload,
pa_legitimate_address_p canonicalizes the order of the
@@ -5978,7 +5978,7 @@ pa_output_arg_descriptor (rtx_insn *call_insn)
rtx use = XEXP (link, 0);
if (! (GET_CODE (use) == USE
- && GET_CODE (XEXP (use, 0)) == REG
+ && REG_P (XEXP (use, 0))
&& FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
continue;
@@ -7612,7 +7612,7 @@ copy_fp_args (rtx_insn *insn)
rtx use = XEXP (link, 0);
if (! (GET_CODE (use) == USE
- && GET_CODE (XEXP (use, 0)) == REG
+ && REG_P (XEXP (use, 0))
&& FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
continue;
@@ -7655,7 +7655,7 @@ length_fp_args (rtx_insn *insn)
rtx use = XEXP (link, 0);
if (! (GET_CODE (use) == USE
- && GET_CODE (XEXP (use, 0)) == REG
+ && REG_P (XEXP (use, 0))
&& FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
continue;
@@ -8674,11 +8674,11 @@ pa_fmpyaddoperands (rtx *operands)
return 0;
/* All operands must be registers. */
- if (! (GET_CODE (operands[1]) == REG
- && GET_CODE (operands[2]) == REG
- && GET_CODE (operands[3]) == REG
- && GET_CODE (operands[4]) == REG
- && GET_CODE (operands[5]) == REG))
+ if (! (REG_P (operands[1])
+ && REG_P (operands[2])
+ && REG_P (operands[3])
+ && REG_P (operands[4])
+ && REG_P (operands[5])))
return 0;
/* Only 2 real operands to the addition. One of the input operands must
@@ -8852,11 +8852,11 @@ pa_fmpysuboperands (rtx *operands)
return 0;
/* All operands must be registers. */
- if (! (GET_CODE (operands[1]) == REG
- && GET_CODE (operands[2]) == REG
- && GET_CODE (operands[3]) == REG
- && GET_CODE (operands[4]) == REG
- && GET_CODE (operands[5]) == REG))
+ if (! (REG_P (operands[1])
+ && REG_P (operands[2])
+ && REG_P (operands[3])
+ && REG_P (operands[4])
+ && REG_P (operands[5])))
return 0;
/* Only 2 real operands to the subtraction. Subtraction is not a commutative
@@ -10616,7 +10616,7 @@ pa_legitimize_reload_address (rtx ad, machine_mode mode,
if (optimize
&& GET_CODE (new_rtx) == PLUS
- && GET_CODE (XEXP (new_rtx, 0)) == REG
+ && REG_P (XEXP (new_rtx, 0))
&& CONST_INT_P (XEXP (new_rtx, 1)))
{
offset = INTVAL (XEXP ((new_rtx), 1));
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 0ce8b635411..01c778368cd 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -6953,7 +6953,7 @@
""
"
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[0] = force_reg (SImode, operands[0]);
if (operands[1] != const0_rtx)
@@ -9668,7 +9668,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
}
operands[2] = gen_reg_rtx (SImode);
- if (GET_CODE (operands[1]) != REG)
+ if (!REG_P (operands[1]))
{
rtx tmp = gen_reg_rtx (Pmode);
emit_move_insn (tmp, operands[1]);
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 4fcd9ed33d5..7a3e24a1b1f 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -797,7 +797,7 @@ pdp11_asm_print_operand (FILE *file, rtx x, int code)
else
fprintf (file, "@");
}
- else if (GET_CODE (x) == REG)
+ else if (REG_P (x))
fprintf (file, "%s", reg_names[REGNO (x)]);
else if (GET_CODE (x) == MEM)
output_address (GET_MODE (x), XEXP (x, 0));
@@ -879,17 +879,17 @@ print_operand_address (FILE *file, register rtx addr)
}
if (GET_CODE (addr) != PLUS)
;
- else if (GET_CODE (XEXP (addr, 0)) == REG)
+ else if (REG_P (XEXP (addr, 0)))
{
breg = XEXP (addr, 0);
addr = XEXP (addr, 1);
}
- else if (GET_CODE (XEXP (addr, 1)) == REG)
+ else if (REG_P (XEXP (addr, 1)))
{
breg = XEXP (addr, 1);
addr = XEXP (addr, 0);
}
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
{
gcc_assert (breg == 0);
breg = addr;
@@ -904,7 +904,7 @@ print_operand_address (FILE *file, register rtx addr)
output_addr_const_pdp11 (file, addr);
if (breg != 0)
{
- gcc_assert (GET_CODE (breg) == REG);
+ gcc_assert (REG_P (breg));
fprintf (file, "(%s)", reg_names[REGNO (breg)]);
}
break;
@@ -1143,7 +1143,7 @@ pdp11_addr_cost (rtx addr, machine_mode mode, addr_space_t as ATTRIBUTE_UNUSED,
{
int cost = 0;
- if (GET_CODE (addr) != REG)
+ if (!REG_P (addr))
{
if (!simple_memory_operand (addr, mode))
cost = 2;
@@ -1376,7 +1376,7 @@ simple_memory_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED)
-- except for @(R0), which has to be @0(R0) !!! */
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
return 0;
op=addr;
@@ -1433,7 +1433,7 @@ no_side_effect_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED)
-- except for @(R0), which has to be @0(R0) !!! */
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
return 0;
op=addr;
@@ -1587,7 +1587,7 @@ pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED,
machine_mode reload_mode ATTRIBUTE_UNUSED,
secondary_reload_info *sri ATTRIBUTE_UNUSED)
{
- if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG ||
+ if (reload_class != NO_LOAD_FPU_REGS || !REG_P (x) ||
REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS)
return NO_REGS;
@@ -1634,36 +1634,36 @@ pdp11_legitimate_address_p (machine_mode mode,
case PLUS:
/* accept X(R0) */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))))
&& CONSTANT_ADDRESS_P (XEXP (operand, 1));
case PRE_DEC:
/* accept -(R0) */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
case POST_INC:
/* accept (R0)+ */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
case PRE_MODIFY:
/* accept -(SP) -- which uses PRE_MODIFY for byte mode */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
&& GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
- && GET_CODE (XEXP (xfoob, 0)) == REG
+ && REG_P (XEXP (xfoob, 0))
&& REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
&& CONST_INT_P (XEXP (xfoob, 1))
&& INTVAL (XEXP (xfoob,1)) == -2;
case POST_MODIFY:
/* accept (SP)+ -- which uses POST_MODIFY for byte mode */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
&& GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
- && GET_CODE (XEXP (xfoob, 0)) == REG
+ && REG_P (XEXP (xfoob, 0))
&& REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
&& CONST_INT_P (XEXP (xfoob, 1))
&& INTVAL (XEXP (xfoob,1)) == 2;
@@ -1694,18 +1694,18 @@ pdp11_legitimate_address_p (machine_mode mode,
case PLUS:
/* accept @X(R0) */
- return GET_CODE (XEXP (xfoob, 0)) == REG
+ return REG_P (XEXP (xfoob, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))))
&& CONSTANT_ADDRESS_P (XEXP (xfoob, 1));
case PRE_DEC:
/* accept @-(R0) */
- return GET_CODE (XEXP (xfoob, 0)) == REG
+ return REG_P (XEXP (xfoob, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
case POST_INC:
/* accept @(R0)+ */
- return GET_CODE (XEXP (xfoob, 0)) == REG
+ return REG_P (XEXP (xfoob, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
default:
diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md
index 3b3815d19aa..e60e9f7d580 100644
--- a/gcc/config/pdp11/pdp11.md
+++ b/gcc/config/pdp11/pdp11.md
@@ -611,7 +611,7 @@
(match_dup 1))
(clobber (reg:CC FCC_REGNUM))])]
"{
- if (GET_CODE (operands[1]) == REG &&
+ if (REG_P (operands[1]) &&
REGNO_REG_CLASS (REGNO (operands[1])) == LOAD_FPU_REGS)
FAIL;
}"
@@ -777,8 +777,8 @@
[(parallel [(set (match_dup 0) (float_truncate:SF (match_dup 1)))
(clobber (reg:CC FCC_REGNUM))])]
"{
- if (GET_CODE (operands[0]) == REG &&
- GET_CODE (operands[1]) == REG &&
+ if (REG_P (operands[0]) &&
+ REG_P (operands[1]) &&
REGNO (operands[0]) == REGNO (operands[1]))
FAIL;
}"
@@ -852,8 +852,8 @@
[(parallel [(set (match_dup 0) (float_extend:DF (match_dup 1)))
(clobber (reg:CC FCC_REGNUM))])]
"{
- if (GET_CODE (operands[0]) == REG &&
- GET_CODE (operands[1]) == REG &&
+ if (REG_P (operands[0]) &&
+ REG_P (operands[1]) &&
REGNO (operands[0]) == REGNO (operands[1]))
FAIL;
}"
diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md
index 568d6f3fa91..a14c77373fc 100644
--- a/gcc/config/pru/predicates.md
+++ b/gcc/config/pru/predicates.md
@@ -198,7 +198,7 @@
/* Perform a quick check so we don't blow up below. */
if (GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+ || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
return false;
@@ -207,7 +207,7 @@
elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
base_reg = strip_offset (src_addr, &base_offs);
- if (GET_CODE (base_reg) != REG)
+ if (!REG_P (base_reg))
return false;
for (i = 1; i < count; i++)
@@ -217,7 +217,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != elt_mode
|| REGNO (SET_DEST (elt)) != dest_regno + i * GET_MODE_SIZE (elt_mode)
|| GET_CODE (SET_SRC (elt)) != MEM
@@ -226,7 +226,7 @@
elt_reg = strip_offset (XEXP (SET_SRC (elt), 0), &elt_offs);
- if (GET_CODE (elt_reg) != REG
+ if (!REG_P (elt_reg)
|| ! rtx_equal_p (elt_reg, base_reg)
|| elt_offs != base_offs + i * GET_MODE_SIZE (elt_mode))
return false;
@@ -251,7 +251,7 @@
/* Perform a quick check so we don't blow up below. */
if (GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+ || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return false;
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -259,7 +259,7 @@
elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
base_reg = strip_offset (dest_addr, &base_offs);
- if (GET_CODE (base_reg) != REG)
+ if (!REG_P (base_reg))
return false;
for (i = 1; i < count; i++)
@@ -269,7 +269,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
+ || !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != elt_mode
|| REGNO (SET_SRC (elt)) != src_regno + i * GET_MODE_SIZE (elt_mode)
|| GET_CODE (SET_DEST (elt)) != MEM
@@ -278,7 +278,7 @@
elt_reg = strip_offset (XEXP (SET_DEST (elt), 0), &elt_offs);
- if (GET_CODE (elt_reg) != REG
+ if (!REG_P (elt_reg)
|| ! rtx_equal_p (elt_reg, base_reg)
|| elt_offs != base_offs + i * GET_MODE_SIZE (elt_mode))
return false;
diff --git a/gcc/config/pru/pru.c b/gcc/config/pru/pru.c
index 0cae5c5cfb7..971428e65bc 100644
--- a/gcc/config/pru/pru.c
+++ b/gcc/config/pru/pru.c
@@ -1090,7 +1090,7 @@ pru_output_ltle_signed_cbranch (rtx *operands, bool is_near)
op1 = operands[1];
op2 = operands[2];
- gcc_assert (GET_CODE (op1) == REG && GET_CODE (op2) == REG);
+ gcc_assert (REG_P (op1) && REG_P (op2));
/* Determine the comparison operators for positive and negative operands. */
if (code == LT)
@@ -1147,7 +1147,7 @@ pru_output_gtge_signed_cbranch (rtx *operands, bool is_near)
op1 = operands[1];
op2 = operands[2];
- gcc_assert (GET_CODE (op1) == REG && GET_CODE (op2) == REG);
+ gcc_assert (REG_P (op1) && REG_P (op2));
/* Determine the comparison operators for positive and negative operands. */
if (code == GT)
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 03527d7def8..c1cb98f5001 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -232,7 +232,7 @@
memory. */
if (!CONST_INT_P (operands[2])
|| GET_CODE (operands[1]) != MEM
- || GET_CODE (operands[0]) != REG)
+ || !REG_P (operands[0]))
FAIL;
count = INTVAL (operands[2]);
@@ -246,7 +246,7 @@
gcc_assert (!can_create_pseudo_p ());
base_reg = strip_offset (XEXP (operands[1], 0), &base_offs);
- if (GET_CODE (base_reg) != REG)
+ if (!REG_P (base_reg))
FAIL;
for (i = 0; i < count; i++)
@@ -290,7 +290,7 @@
memory. */
if (!CONST_INT_P (operands[2])
|| GET_CODE (operands[0]) != MEM
- || GET_CODE (operands[1]) != REG)
+ || !REG_P (operands[1]))
FAIL;
count = INTVAL (operands[2]);
@@ -304,7 +304,7 @@
gcc_assert (!can_create_pseudo_p ());
base_reg = strip_offset (XEXP (operands[0], 0), &base_offs);
- if (GET_CODE (base_reg) != REG)
+ if (!REG_P (base_reg))
FAIL;
for (i = 0; i < count; i++)
@@ -945,7 +945,7 @@
(use (label_ref (match_operand 1 "")))]
"TARGET_OPT_LOOP"
{
- if (GET_CODE (operands[0]) == REG && GET_MODE (operands[0]) == QImode)
+ if (REG_P (operands[0]) && GET_MODE (operands[0]) == QImode)
FAIL;
pru_emit_doloop (operands, 1);
DONE;
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 40faf0e0380..6cc134df900 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -64,7 +64,7 @@
(define_memory_constraint "A"
"An address that is held in a general-purpose register."
(and (match_code "mem")
- (match_test "GET_CODE(XEXP(op,0)) == REG")))
+ (match_test "REG_P (XEXP(op,0))")))
(define_constraint "S"
"@internal
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index ada45f5bf54..f3f7ecb4b22 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -931,7 +931,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
&& XINT (x, 1) == UNS_ES_ADDR)
x = XVECEXP (x, 0, 1);
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
*base = x;
return true;
@@ -955,7 +955,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
{
if (GET_MODE (*base) == HImode
&& GET_MODE (XEXP (*base, 0)) == SImode
- && GET_CODE (XEXP (*base, 0)) == REG)
+ && REG_P (XEXP (*base, 0)))
{
/* This is a throw-away rtx just to tell everyone
else what effective register we're using. */
@@ -963,19 +963,19 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
}
}
- if (GET_CODE (*base) != REG
- && GET_CODE (x) == REG)
+ if (!REG_P (*base)
+ && REG_P (x))
{
rtx tmp = *base;
*base = x;
x = tmp;
}
- if (GET_CODE (*base) != REG)
+ if (!REG_P (*base))
return false;
if (GET_CODE (x) == ZERO_EXTEND
- && GET_CODE (XEXP (x, 0)) == REG)
+ && REG_P (XEXP (x, 0)))
{
*index = XEXP (x, 0);
return false;
@@ -1038,12 +1038,12 @@ rl78_hl_b_c_addr_p (rtx op)
hl = bc;
bc = tmp;
}
- if (GET_CODE (hl) != REG)
+ if (!REG_P (hl))
return false;
if (GET_CODE (bc) != ZERO_EXTEND)
return false;
bc = XEXP (bc, 0);
- if (GET_CODE (bc) != REG)
+ if (!REG_P (bc))
return false;
if (REGNO (hl) != HL_REG)
return false;
@@ -1182,10 +1182,10 @@ rl78_as_legitimate_address (machine_mode mode ATTRIBUTE_UNUSED, rtx x,
return false;
}
- if (strict && base && GET_CODE (base) == REG && REGNO (base) >= FIRST_PSEUDO_REGISTER)
+ if (strict && base && REG_P (base) && REGNO (base) >= FIRST_PSEUDO_REGISTER)
return false;
- if (! cfun->machine->virt_insns_ok && base && GET_CODE (base) == REG
+ if (! cfun->machine->virt_insns_ok && base && REG_P (base)
&& REGNO (base) >= 8 && REGNO (base) <= 31)
return false;
@@ -1233,7 +1233,7 @@ rl78_addr_space_convert (rtx op, tree from_type, tree to_type)
warning (OPT_Waddress, "converting far pointer to near pointer");
result = gen_reg_rtx (HImode);
if (GET_CODE (op) == SYMBOL_REF
- || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER))
+ || (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
tmp = gen_rtx_raw_SUBREG (HImode, op, 0);
else
tmp = simplify_subreg (HImode, op, SImode, 0);
@@ -1873,13 +1873,13 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
rl78_print_operand_1 (file, XEXP (op, 0), letter);
}
else if (GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (op, 0), 0))
&& REGNO (XEXP (XEXP (op, 0), 0)) == 2)
{
rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 1), 'u');
fprintf (file, "[");
rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 0), 0);
- if (letter == 'p' && GET_CODE (XEXP (op, 0)) == REG)
+ if (letter == 'p' && REG_P (XEXP (op, 0)))
fprintf (file, "+0");
fprintf (file, "]");
}
@@ -1979,7 +1979,7 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
break;
case ZERO_EXTEND:
- if (GET_CODE (XEXP (op, 0)) == REG)
+ if (REG_P (XEXP (op, 0)))
fprintf (file, "%s", reg_names [REGNO (XEXP (op, 0))]);
else
print_rtl (file, op);
@@ -2269,7 +2269,7 @@ rl78_peep_movhi_p (rtx *operands)
/* You can move a constant to memory as QImode, but not HImode. */
if (GET_CODE (operands[0]) == MEM
- && GET_CODE (operands[1]) != REG)
+ && !REG_P (operands[1]))
{
#if DEBUG_PEEP
fprintf (stderr, "no peep: move constant to memory\n");
@@ -2812,7 +2812,7 @@ insn_ok_now (rtx_insn * insn)
static inline bool
is_virtual_register (rtx r)
{
- return (GET_CODE (r) == REG
+ return (REG_P (r)
&& REGNO (r) >= 8
&& REGNO (r) < 32);
}
@@ -3643,7 +3643,7 @@ rl78_alloc_address_registers_macax (rtx_insn * insn)
OP (op) = transcode_memory_rtx (OP (op), HL, insn);
if (op == 2
&& MEM_P (OP (op))
- && ((GET_CODE (XEXP (OP (op), 0)) == REG
+ && ((REG_P (XEXP (OP (op), 0))
&& REGNO (XEXP (OP (op), 0)) == SP_REG)
|| (GET_CODE (XEXP (OP (op), 0)) == PLUS
&& REGNO (XEXP (XEXP (OP (op), 0), 0)) == SP_REG)))
@@ -3904,7 +3904,7 @@ rl78_note_reg_set (char *dead, rtx d, rtx insn)
if (GET_CODE (d) == MEM)
rl78_note_reg_uses (dead, XEXP (d, 0), insn);
- if (GET_CODE (d) != REG)
+ if (!REG_P (d))
return;
/* Do not mark the reg unused unless all QImode parts of it are dead. */
@@ -4030,11 +4030,11 @@ set_origin (rtx pat, rtx_insn * insn, int * origins, int * age)
int mb = GET_MODE_SIZE (GET_MODE (dest));
int i;
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int dr = REGNO (dest);
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int sr = REGNO (src);
bool same = true;
@@ -4173,7 +4173,7 @@ set_origin (rtx pat, rtx_insn * insn, int * origins, int * age)
{
rtx count = XEXP (src, 1);
- if (GET_CODE (count) == REG)
+ if (REG_P (count))
{
/* Special case - our pattern clobbers the count register. */
int r = REGNO (count);
@@ -4245,7 +4245,7 @@ rl78_propogate_register_origins (void)
rtx clobber = XVECEXP (pat, 0, 1);
pat = XVECEXP (pat, 0, 0);
if (GET_CODE (clobber) == CLOBBER
- && GET_CODE (XEXP (clobber, 0)) == REG)
+ && REG_P (XEXP (clobber, 0)))
{
int cr = REGNO (XEXP (clobber, 0));
int mb = GET_MODE_SIZE (GET_MODE (XEXP (clobber, 0)));
@@ -4271,7 +4271,7 @@ rl78_propogate_register_origins (void)
set_origin (pat, insn, origins, age);
}
else if (GET_CODE (pat) == CLOBBER
- && GET_CODE (XEXP (pat, 0)) == REG)
+ && REG_P (XEXP (pat, 0)))
{
if (REG_P (XEXP (pat, 0)))
{
@@ -4302,7 +4302,7 @@ rl78_remove_unused_sets (void)
dest = SET_DEST (set);
- if (GET_CODE (dest) != REG || REGNO (dest) > 23)
+ if (!REG_P (dest) || REGNO (dest) > 23)
continue;
if (find_regno_note (insn, REG_UNUSED, REGNO (dest)))
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index 905d3054de2..ea04eb6b836 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -120,7 +120,7 @@ rx_pid_data_operand (rtx op)
return PID_NOT_PID;
if (GET_CODE (op) == PLUS
- && GET_CODE (XEXP (op, 0)) == REG
+ && REG_P (XEXP (op, 0))
&& GET_CODE (XEXP (op, 1)) == CONST
&& GET_CODE (XEXP (XEXP (op, 1), 0)) == UNSPEC)
return PID_ENCODED;
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index 7065be69e43..3060e59cbc6 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -578,7 +578,7 @@
operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
operands[0] = rx_maybe_pidify_operand (operands[0], 0);
operands[1] = rx_maybe_pidify_operand (operands[1], 0);
- if (GET_CODE (operands[0]) != REG
+ if (!REG_P (operands[0])
&& GET_CODE (operands[1]) == PLUS)
operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
if (GET_CODE (operands[1]) == PLUS && GET_MODE (operands[1]) == SImode)
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index 15758fb731a..aec2de30219 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -244,7 +244,7 @@
uneq, unlt, ungt, unle, unge, ltgt,
unordered, ordered")
{
- if (GET_CODE (XEXP (op, 0)) != REG
+ if (!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM
|| (XEXP (op, 1) != const0_rtx
&& !(CONST_INT_P (XEXP (op, 1))
@@ -296,7 +296,7 @@
if (!COMPARISON_P (op))
return false;
- if (GET_CODE (XEXP (op, 0)) != REG
+ if (!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM
|| (XEXP (op, 1) != const0_rtx
&& !(CONST_INT_P (XEXP (op, 1))
@@ -345,7 +345,7 @@
if (!COMPARISON_P (op))
return false;
- if (GET_CODE (XEXP (op, 0)) != REG
+ if (!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM
|| XEXP (op, 1) != const0_rtx)
return false;
@@ -393,7 +393,7 @@
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+ || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
return false;
@@ -403,10 +403,10 @@
/* Check, is base, or base + displacement. */
- if (GET_CODE (src_addr) == REG)
+ if (REG_P (src_addr))
off = 0;
else if (GET_CODE (src_addr) == PLUS
- && GET_CODE (XEXP (src_addr, 0)) == REG
+ && REG_P (XEXP (src_addr, 0))
&& CONST_INT_P (XEXP (src_addr, 1)))
{
off = INTVAL (XEXP (src_addr, 1));
@@ -420,7 +420,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != elt_mode
|| REGNO (SET_DEST (elt)) != dest_regno + i
|| GET_CODE (SET_SRC (elt)) != MEM
@@ -497,7 +497,7 @@
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+ || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return false;
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -506,10 +506,10 @@
/* Check, is base, or base + displacement. */
- if (GET_CODE (dest_addr) == REG)
+ if (REG_P (dest_addr))
off = 0;
else if (GET_CODE (dest_addr) == PLUS
- && GET_CODE (XEXP (dest_addr, 0)) == REG
+ && REG_P (XEXP (dest_addr, 0))
&& CONST_INT_P (XEXP (dest_addr, 1)))
{
off = INTVAL (XEXP (dest_addr, 1));
@@ -523,7 +523,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
+ || !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != elt_mode
|| REGNO (SET_SRC (elt)) != src_regno + i
|| GET_CODE (SET_DEST (elt)) != MEM
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 31fc179645d..a61c7d5ed79 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -1367,7 +1367,7 @@ s390_match_ccmode_set (rtx set, machine_mode req_mode)
gcc_assert (req_mode != CCVIALLmode && req_mode != CCVIANYmode
&& req_mode != CCVFALLmode && req_mode != CCVFANYmode);
- if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
+ if (!REG_P (SET_DEST (set)) || !CC_REGNO_P (REGNO (SET_DEST (set))))
return 1;
set_mode = GET_MODE (SET_DEST (set));
@@ -1688,7 +1688,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
&& XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT
&& XVECLEN (*op0, 0) == 1
&& GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
- && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
+ && REG_P (XVECEXP (*op0, 0, 0))
&& REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
&& *op1 == const0_rtx)
{
@@ -1715,7 +1715,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
if (GET_CODE (*op0) == UNSPEC
&& XINT (*op0, 1) == UNSPEC_CC_TO_INT
&& XVECLEN (*op0, 0) == 1
- && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
+ && REG_P (XVECEXP (*op0, 0, 0))
&& REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
&& CONST_INT_P (*op1))
{
@@ -1935,7 +1935,7 @@ s390_branch_condition_mask (rtx code)
const int CC2 = 1 << 1;
const int CC3 = 1 << 0;
- gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
+ gcc_assert (REG_P (XEXP (code, 0)));
gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
gcc_assert (XEXP (code, 1) == const0_rtx
|| (GET_MODE (XEXP (code, 0)) == CCRAWmode
@@ -2249,7 +2249,7 @@ s390_branch_condition_mnemonic (rtx code, int inv)
"le", "nh", "no", NULL
};
- if (GET_CODE (XEXP (code, 0)) == REG
+ if (REG_P (XEXP (code, 0))
&& REGNO (XEXP (code, 0)) == CC_REGNUM
&& (XEXP (code, 1) == const0_rtx
|| (GET_MODE (XEXP (code, 0)) == CCRAWmode
@@ -2901,7 +2901,7 @@ s390_decompose_address (rtx addr, struct s390_address *out)
/* Decompose address into base + index + displacement. */
- if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
+ if (REG_P (addr) || GET_CODE (addr) == UNSPEC)
base = addr;
else if (GET_CODE (addr) == PLUS)
@@ -3119,7 +3119,7 @@ s390_decompose_addrstyle_without_index (rtx op, rtx *base,
while (op && GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
- if (op && GET_CODE (op) != REG)
+ if (op && !REG_P (op))
return false;
if (offset)
@@ -5371,7 +5371,7 @@ s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
if (GET_CODE (x) == PLUS)
{
- if (GET_CODE (XEXP (x, 0)) == REG)
+ if (REG_P (XEXP (x, 0)))
{
rtx temp = gen_reg_rtx (Pmode);
rtx val = force_operand (XEXP (x, 1), temp);
@@ -5381,7 +5381,7 @@ s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
}
- else if (GET_CODE (XEXP (x, 1)) == REG)
+ else if (REG_P (XEXP (x, 1)))
{
rtx temp = gen_reg_rtx (Pmode);
rtx val = force_operand (XEXP (x, 0), temp);
@@ -5420,7 +5420,7 @@ legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED,
}
if (GET_CODE (ad) == PLUS
- && GET_CODE (XEXP (ad, 0)) == REG
+ && REG_P (XEXP (ad, 0))
&& CONST_INT_P (XEXP (ad, 1))
&& !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
{
@@ -7435,7 +7435,7 @@ s390_delegitimize_address (rtx orig_x)
x = XEXP (x, 0);
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 1)) == CONST
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
{
y = XEXP (XEXP (x, 1), 0);
@@ -7490,7 +7490,7 @@ print_addrstyle_operand (FILE *file, rtx op)
/* Sanity check. */
if (base)
{
- gcc_assert (GET_CODE (base) == REG);
+ gcc_assert (REG_P (base));
gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
}
@@ -7964,7 +7964,7 @@ print_operand (FILE *file, rtx x, int code)
return;
case 'N':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
else if (GET_CODE (x) == MEM)
x = change_address (x, VOIDmode,
@@ -7975,7 +7975,7 @@ print_operand (FILE *file, rtx x, int code)
break;
case 'M':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
else if (GET_CODE (x) == MEM)
x = change_address (x, VOIDmode,
@@ -8211,7 +8211,7 @@ addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn)
while (GET_CODE (target) == SUBREG)
target = SUBREG_REG (target);
- if (GET_CODE (target) == REG)
+ if (REG_P (target))
{
int regno = REGNO (target);
@@ -13712,7 +13712,7 @@ s390_optimize_prologue (void)
base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
off = INTVAL (offset);
- if (GET_CODE (base) != REG || off < 0)
+ if (!REG_P (base) || off < 0)
continue;
if (cfun_frame_layout.first_save_gpr != -1
&& (cfun_frame_layout.first_save_gpr < first
@@ -13750,7 +13750,7 @@ s390_optimize_prologue (void)
base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
off = INTVAL (offset);
- if (GET_CODE (base) != REG || off < 0)
+ if (!REG_P (base) || off < 0)
continue;
if (REGNO (base) != STACK_POINTER_REGNUM
&& REGNO (base) != HARD_FRAME_POINTER_REGNUM)
@@ -13770,7 +13770,7 @@ s390_optimize_prologue (void)
base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
off = INTVAL (offset);
- if (GET_CODE (base) != REG || off < 0)
+ if (!REG_P (base) || off < 0)
continue;
if (cfun_frame_layout.first_restore_gpr != -1
@@ -13821,7 +13821,7 @@ s390_optimize_prologue (void)
base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
off = INTVAL (offset);
- if (GET_CODE (base) != REG || off < 0)
+ if (!REG_P (base) || off < 0)
continue;
if (REGNO (base) != STACK_POINTER_REGNUM
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index a50090af0a1..0f2cc5a7752 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2841,7 +2841,7 @@
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > 16
|| GET_CODE (operands[1]) != MEM
- || GET_CODE (operands[0]) != REG
+ || !REG_P (operands[0])
|| REGNO (operands[0]) >= 16)
FAIL;
@@ -2854,13 +2854,13 @@
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
if (!can_create_pseudo_p ())
{
- if (GET_CODE (XEXP (operands[1], 0)) == REG)
+ if (REG_P (XEXP (operands[1], 0)))
{
from = XEXP (operands[1], 0);
off = 0;
}
else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
- && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
+ && REG_P (XEXP (XEXP (operands[1], 0), 0))
&& CONST_INT_P (XEXP (XEXP (operands[1], 0), 1)))
{
from = XEXP (XEXP (operands[1], 0), 0);
@@ -2932,7 +2932,7 @@
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > 16
|| GET_CODE (operands[0]) != MEM
- || GET_CODE (operands[1]) != REG
+ || !REG_P (operands[1])
|| REGNO (operands[1]) >= 16)
FAIL;
@@ -2946,13 +2946,13 @@
if (!can_create_pseudo_p ())
{
- if (GET_CODE (XEXP (operands[0], 0)) == REG)
+ if (REG_P (XEXP (operands[0], 0)))
{
to = XEXP (operands[0], 0);
off = 0;
}
else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
- && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
+ && REG_P (XEXP (XEXP (operands[0], 0), 0))
&& CONST_INT_P (XEXP (XEXP (operands[0], 0), 1)))
{
to = XEXP (XEXP (operands[0], 0), 0);
@@ -10092,7 +10092,7 @@
if (Pmode != SImode)
index = convert_to_mode (Pmode, index, 1);
- if (GET_CODE (index) != REG)
+ if (!REG_P (index))
index = copy_to_mode_reg (Pmode, index);
if (TARGET_64BIT)
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 7326d83a96f..df371584f9e 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -3490,8 +3490,8 @@ emit_scc_insn (rtx operands[])
back to the easy case. */
if (code == GTU || code == LEU)
{
- if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
- && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
+ if ((REG_P (x) || GET_CODE (x) == SUBREG)
+ && (REG_P (y) || GET_CODE (y) == SUBREG))
{
tem = x;
x = y;
@@ -3570,7 +3570,7 @@ emit_conditional_branch_insn (rtx operands[])
that won't fit in the 5-bit signed immediate field of a cbcond,
use one of the other v9 conditional branch sequences. */
if (TARGET_CBCOND
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& (GET_MODE (operands[1]) == SImode
|| (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode))
&& (!CONST_INT_P (operands[2])
@@ -3581,7 +3581,7 @@ emit_conditional_branch_insn (rtx operands[])
}
if (TARGET_ARCH64 && operands[2] == const0_rtx
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& GET_MODE (operands[1]) == DImode)
{
emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
@@ -4018,7 +4018,7 @@ eligible_for_restore_insn (rtx trial, bool return_p)
src_reg = src;
if (GET_CODE (src_reg) == SUBREG)
src_reg = SUBREG_REG (src_reg);
- if (GET_CODE (src_reg) == REG
+ if (REG_P (src_reg)
&& SPARC_FP_REG_P (REGNO (src_reg)))
src_is_freg = true;
@@ -4119,7 +4119,7 @@ eligible_for_return_delay (rtx_insn *trial)
rtx expr = XVECEXP (pat, 0, i);
if (GET_CODE (expr) != SET)
return 0;
- if (GET_CODE (SET_DEST (expr)) != REG)
+ if (!REG_P (SET_DEST (expr)))
return 0;
regno = REGNO (SET_DEST (expr));
if (regno >= 8 && regno < 24)
@@ -4131,7 +4131,7 @@ eligible_for_return_delay (rtx_insn *trial)
if (GET_CODE (pat) != SET)
return 0;
- if (GET_CODE (SET_DEST (pat)) != REG)
+ if (!REG_P (SET_DEST (pat)))
return 0;
regno = REGNO (SET_DEST (pat));
@@ -4184,7 +4184,7 @@ eligible_for_sibcall_delay (rtx_insn *trial)
/* Otherwise, only operations which can be done in tandem with
a `restore' insn can go into the delay slot. */
- if (GET_CODE (SET_DEST (pat)) != REG
+ if (!REG_P (SET_DEST (pat))
|| (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
|| ! SPARC_INT_REG_P (REGNO (SET_DEST (pat))))
return 0;
@@ -5174,7 +5174,7 @@ mem_min_alignment (rtx mem, int desired)
base = offset = NULL_RTX;
if (GET_CODE (addr) == PLUS)
{
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
{
base = XEXP (addr, 0);
@@ -5188,7 +5188,7 @@ mem_min_alignment (rtx mem, int desired)
offset = const0_rtx;
}
}
- else if (GET_CODE (addr) == REG)
+ else if (REG_P (addr))
{
base = addr;
offset = const0_rtx;
@@ -8908,7 +8908,7 @@ epilogue_renumber (register rtx *where, int test)
are in the return delayed slot. */
case PLUS:
- if (GET_CODE (XEXP (*where, 0)) == REG
+ if (REG_P (XEXP (*where, 0))
&& REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
&& (!CONST_INT_P (XEXP (*where, 1))
|| INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
@@ -8917,7 +8917,7 @@ epilogue_renumber (register rtx *where, int test)
case MEM:
if (SPARC_STACK_BIAS
- && GET_CODE (XEXP (*where, 0)) == REG
+ && REG_P (XEXP (*where, 0))
&& REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
return 1;
break;
@@ -9038,13 +9038,13 @@ sparc_split_reg_reg_legitimate (rtx reg1, rtx reg2)
if (GET_CODE (reg1) == SUBREG)
reg1 = SUBREG_REG (reg1);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
return 0;
const int regno1 = REGNO (reg1);
if (GET_CODE (reg2) == SUBREG)
reg2 = SUBREG_REG (reg2);
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
return 0;
const int regno2 = REGNO (reg2);
@@ -9094,7 +9094,7 @@ int
registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
{
/* We might have been passed a SUBREG. */
- if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
+ if (!REG_P (reg1) || !REG_P (reg2))
return 0;
if (REGNO (reg1) % 2 != 0)
@@ -9160,7 +9160,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
if (GET_CODE (addr1) == PLUS)
{
/* If not a REG, return zero. */
- if (GET_CODE (XEXP (addr1, 0)) != REG)
+ if (!REG_P (XEXP (addr1, 0)))
return 0;
else
{
@@ -9171,7 +9171,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
offset1 = INTVAL (XEXP (addr1, 1));
}
}
- else if (GET_CODE (addr1) != REG)
+ else if (!REG_P (addr1))
return 0;
else
{
@@ -9184,7 +9184,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
if (GET_CODE (addr2) != PLUS)
return 0;
- if (GET_CODE (XEXP (addr2, 0)) != REG
+ if (!REG_P (XEXP (addr2, 0))
|| !CONST_INT_P (XEXP (addr2, 1)))
return 0;
@@ -9343,7 +9343,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
/* Adjust the operand to take into account a RESTORE operation. */
if (CONST_INT_P (x))
break;
- else if (GET_CODE (x) != REG)
+ else if (!REG_P (x))
output_operand_lossage ("invalid %%Y operand");
else if (REGNO (x) < 8)
fputs (reg_names[REGNO (x)], file);
@@ -9617,7 +9617,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
output_operand_lossage ("invalid operand output code");
}
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names[REGNO (x)], file);
else if (GET_CODE (x) == MEM)
{
@@ -10316,22 +10316,22 @@ set_extends (rtx_insn *insn)
rtx op1 = XEXP (SET_SRC (pat), 1);
if (CONST_INT_P (op1))
return INTVAL (op1) >= 0;
- if (GET_CODE (op0) != REG)
+ if (!REG_P (op0))
return 0;
if (sparc_check_64 (op0, insn) == 1)
return 1;
- return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
+ return (REG_P (op1) && sparc_check_64 (op1, insn) == 1);
}
case IOR:
case XOR:
{
rtx op0 = XEXP (SET_SRC (pat), 0);
rtx op1 = XEXP (SET_SRC (pat), 1);
- if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
+ if (!REG_P (op0) || sparc_check_64 (op0, insn) <= 0)
return 0;
if (CONST_INT_P (op1))
return INTVAL (op1) >= 0;
- return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
+ return (REG_P (op1) && sparc_check_64 (op1, insn) == 1);
}
case LSHIFTRT:
return GET_MODE (SET_SRC (pat)) == SImode;
@@ -10461,7 +10461,7 @@ sparc_check_64 (rtx x, rtx_insn *insn)
int set_once = 0;
rtx y = x;
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
if (GET_MODE (x) == DImode)
y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
@@ -13403,7 +13403,7 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
if (FP_REG_CLASS_P (rclass)
&& (mode == HImode || mode == QImode)
&& (GET_CODE (x) == MEM
- || ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ || ((REG_P (x) || GET_CODE (x) == SUBREG)
&& true_regnum (x) == -1)))
return GENERAL_REGS;
@@ -13530,7 +13530,7 @@ sparc_expand_conditional_move (machine_mode mode, rtx *operands)
}
if (XEXP (cmp, 1) == const0_rtx
- && GET_CODE (XEXP (cmp, 0)) == REG
+ && REG_P (XEXP (cmp, 0))
&& cmp_mode == DImode
&& v9_regcmp_p (rc))
cc_reg = XEXP (cmp, 0);
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 60220904346..26b7f808e82 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2131,10 +2131,10 @@ visl")
(match_operand:DI 1 "const_int_operand" ""))]
"reload_completed
&& TARGET_ARCH32
- && ((GET_CODE (operands[0]) == REG
+ && ((REG_P (operands[0])
&& SPARC_INT_REG_P (REGNO (operands[0])))
|| (GET_CODE (operands[0]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[0])) == REG
+ && REG_P (SUBREG_REG (operands[0]))
&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
[(clobber (const_int 0))]
{
@@ -2577,10 +2577,10 @@ visl")
(match_operand:DF 1 "const_zero_operand" ""))]
"reload_completed
&& TARGET_ARCH32
- && ((GET_CODE (operands[0]) == REG
+ && ((REG_P (operands[0])
&& SPARC_INT_REG_P (REGNO (operands[0])))
|| (GET_CODE (operands[0]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[0])) == REG
+ && REG_P (SUBREG_REG (operands[0]))
&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
[(clobber (const_int 0))]
{
diff --git a/gcc/config/spu/constraints.md b/gcc/config/spu/constraints.md
index 2a542a7101e..0206d15d9a8 100644
--- a/gcc/config/spu/constraints.md
+++ b/gcc/config/spu/constraints.md
@@ -149,7 +149,7 @@
(define_memory_constraint "R"
"Call operand, reg, for indirect calls"
(and (match_code "mem")
- (match_test "GET_CODE(XEXP(op, 0)) == REG")))
+ (match_test "REG_P (XEXP(op, 0))")))
(define_memory_constraint "S"
"Call operand, symbol, for relative calls."
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index fe893b62a9e..e850c9ba40e 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -1050,7 +1050,7 @@ print_operand_address (FILE * file, register rtx addr)
case PLUS:
reg = XEXP (addr, 0);
offset = XEXP (addr, 1);
- if (GET_CODE (offset) == REG)
+ if (REG_P (offset))
{
fprintf (file, "%s,%s", reg_names[REGNO (reg)],
reg_names[REGNO (offset)]);
@@ -1350,7 +1350,7 @@ print_operand (FILE * file, rtx x, int code)
case 'i': /* indirect call */
if (xcode == MEM)
{
- if (GET_CODE (XEXP (x, 0)) == REG)
+ if (REG_P (XEXP (x, 0)))
/* Used in indirect function calls. */
fprintf (file, "%s", reg_names[REGNO (XEXP (x, 0))]);
else
@@ -1377,7 +1377,7 @@ print_operand (FILE * file, rtx x, int code)
fprintf (file, "r");
else if (xcode == PLUS || xcode == LO_SUM)
{
- if (GET_CODE (XEXP (x, 1)) == REG)
+ if (REG_P (XEXP (x, 1)))
fprintf (file, "x");
else
fprintf (file, "d");
@@ -2253,7 +2253,7 @@ insn_clobbers_hbr (rtx_insn *insn)
{
clobber = XVECEXP (parallel, 0, j);
if (GET_CODE (clobber) == CLOBBER
- && GET_CODE (XEXP (clobber, 0)) == REG
+ && REG_P (XEXP (clobber, 0))
&& REGNO (XEXP (clobber, 0)) == HBR_REGNUM)
return 1;
}
@@ -2508,7 +2508,7 @@ spu_machine_dependent_reorg (void)
{
insn_addr = INSN_ADDRESSES (INSN_UID (insn));
if (branch
- && ((GET_CODE (branch_target) == REG
+ && ((REG_P (branch_target)
&& set_of (branch_target, insn) != NULL_RTX)
|| insn_clobbers_hbr (insn)
|| branch_addr - insn_addr > 600))
@@ -2589,7 +2589,7 @@ spu_machine_dependent_reorg (void)
&& EDGE_COUNT (prev->preds) == 1
&& EDGE_PRED (prev, 0)->src == prev2
&& prev2->loop_father == bb->loop_father
- && GET_CODE (branch_target) != REG)
+ && !REG_P (branch_target))
prop = prev;
/* Don't propagate when:
@@ -3030,7 +3030,7 @@ spu_sched_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
if (CALL_P (insn))
{
rtx target = get_branch_target (insn);
- if (GET_CODE (target) != REG || !set_of (target, insn))
+ if (!REG_P (target) || !set_of (target, insn))
return cost - 2;
return cost;
}
@@ -3045,7 +3045,7 @@ spu_sched_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
issued. */
if (INSN_CODE (insn) == CODE_FOR__return
&& (set = single_set (dep_insn))
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) == LINK_REGISTER_REGNUM)
return 20;
@@ -3555,7 +3555,7 @@ spu_legitimate_address_p (machine_mode mode,
op0 = XEXP (op0, 0);
if (GET_CODE (op1) == SUBREG)
op1 = XEXP (op1, 0);
- if (GET_CODE (op0) == REG
+ if (REG_P (op0)
&& INT_REG_OK_FOR_BASE_P (op0, reg_ok_strict)
&& CONST_INT_P (op1)
&& ((INTVAL (op1) >= -0x2000 && INTVAL (op1) <= 0x1fff)
@@ -3568,9 +3568,9 @@ spu_legitimate_address_p (machine_mode mode,
|| op0 == virtual_stack_vars_rtx)
&& (!aligned || (INTVAL (op1) & 15) == 0))
return TRUE;
- if (GET_CODE (op0) == REG
+ if (REG_P (op0)
&& INT_REG_OK_FOR_BASE_P (op0, reg_ok_strict)
- && GET_CODE (op1) == REG
+ && REG_P (op1)
&& INT_REG_OK_FOR_INDEX_P (op1, reg_ok_strict))
return TRUE;
}
@@ -3613,14 +3613,14 @@ spu_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
op0 = force_reg (Pmode, op0);
mark_reg_pointer (op0, 128);
}
- else if (GET_CODE (op0) != REG)
+ else if (!REG_P (op0))
op0 = force_reg (Pmode, op0);
if (ALIGNED_SYMBOL_REF_P (op1))
{
op1 = force_reg (Pmode, op1);
mark_reg_pointer (op1, 128);
}
- else if (GET_CODE (op1) != REG)
+ else if (!REG_P (op1))
op1 = force_reg (Pmode, op1);
x = gen_rtx_PLUS (Pmode, op0, op1);
}
@@ -4841,7 +4841,7 @@ spu_split_store (rtx * ops)
}
else
{
- if (GET_CODE (ops[1]) == REG)
+ if (REG_P (ops[1]))
emit_insn (gen_spu_convert (reg, ops[1]));
else if (GET_CODE (ops[1]) == SUBREG)
emit_insn (gen_spu_convert (reg, SUBREG_REG (ops[1])));
@@ -4994,9 +4994,9 @@ gen_cpat_const (rtx * ops)
if (!CONST_INT_P (ops[3])
|| !CONST_INT_P (ops[2])
|| (!CONST_INT_P (ops[1])
- && GET_CODE (ops[1]) != REG))
+ && !REG_P (ops[1])))
return 0;
- if (GET_CODE (ops[1]) == REG
+ if (REG_P (ops[1])
&& (!REG_POINTER (ops[1])
|| REGNO_POINTER_ALIGN (ORIGINAL_REGNO (ops[1])) < 128))
return 0;
@@ -5307,7 +5307,7 @@ spu_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
cost =
GET_CODE (XEXP (x, 0)) ==
REG ? COSTS_N_INSNS (12) : COSTS_N_INSNS (7);
- if (mode == SImode && GET_CODE (XEXP (x, 0)) == REG)
+ if (mode == SImode && REG_P (XEXP (x, 0)))
{
if (CONST_INT_P (XEXP (x, 1)))
{
@@ -5661,7 +5661,7 @@ spu_builtin_splats (rtx ops[])
{
rtx reg = gen_reg_rtx (TImode);
rtx shuf;
- if (GET_CODE (ops[1]) != REG
+ if (!REG_P (ops[1])
&& GET_CODE (ops[1]) != SUBREG)
ops[1] = force_reg (GET_MODE_INNER (mode), ops[1]);
switch (mode)
@@ -6450,7 +6450,7 @@ spu_expand_builtin_1 (struct spu_builtin_description *d,
/* Try to use target because not using it can lead to extra copies
and when we are using all of the registers extra copies leads
to extra spills. */
- if (target && GET_CODE (target) == REG && GET_MODE (target) == tmode)
+ if (target && REG_P (target) && GET_MODE (target) == tmode)
ops[0] = target;
else
target = ops[0] = gen_reg_rtx (tmode);
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index ba7858a645f..47705c65067 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -2354,7 +2354,7 @@
rtx op2 = operands[2];
rtx op3 = operands[3];
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
{
emit_insn (gen_addsi3 (op3, op2, GEN_INT (64)));
emit_insn (gen_rotlti3 (op0, op1, GEN_INT (64)));
@@ -2470,7 +2470,7 @@
"@
#
rot<bh>mi\t%0,%1,-%<umask>2"
- "reload_completed && GET_CODE (operands[2]) == REG"
+ "reload_completed && REG_P (operands[2])"
[(set (match_dup:VHSI 3)
(neg:VHSI (match_dup:VHSI 2)))
(set (match_dup:VHSI 0)
@@ -2634,7 +2634,7 @@
"@
#
rotma<bh>i\t%0,%1,-%<umask>2"
- "reload_completed && GET_CODE (operands[2]) == REG"
+ "reload_completed && REG_P (operands[2])"
[(set (match_dup:VHSI 3)
(neg:VHSI (match_dup:VHSI 2)))
(set (match_dup:VHSI 0)
@@ -2714,7 +2714,7 @@
emit_move_insn (op4, array_to_constant (TImode, arr));
emit_insn (gen_spu_fsm (op3v, op5));
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
{
emit_insn (gen_selb (op4, op3, op1, op4));
emit_insn (gen_negsi2 (op5, op2));
diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md
index 66edd7cbe09..a1821a3bc29 100644
--- a/gcc/config/v850/predicates.md
+++ b/gcc/config/v850/predicates.md
@@ -73,7 +73,7 @@
(define_predicate "even_reg_operand"
(match_code "reg")
{
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| ((REGNO (op) > 0) && (REGNO (op) < 32)
&& ((REGNO (op) & 1)==0))));
@@ -86,8 +86,8 @@
{
/* Only registers are valid call operands if TARGET_LONG_CALLS. */
if (TARGET_LONG_CALLS)
- return GET_CODE (op) == REG;
- return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
+ return REG_P (op);
+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op));
})
;; Return true if OP is a valid source operand for SImode move.
@@ -198,7 +198,7 @@
if (GET_CODE (dest) != MEM
|| GET_MODE (dest) != SImode
- || GET_CODE (src) != REG
+ || !REG_P (src)
|| GET_MODE (src) != SImode
|| ! register_is_ok_for_epilogue (src, SImode))
return 0;
@@ -206,7 +206,7 @@
plus = XEXP (dest, 0);
if ( GET_CODE (plus) != PLUS
- || GET_CODE (XEXP (plus, 0)) != REG
+ || !REG_P (XEXP (plus, 0))
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (plus, 1)))
@@ -226,7 +226,7 @@
vector_element = XVECEXP (op, 0, i++);
if (GET_CODE (vector_element) != CLOBBER
- || GET_CODE (XEXP (vector_element, 0)) != REG
+ || !REG_P (XEXP (vector_element, 0))
|| REGNO (XEXP (vector_element, 0)) != 10)
return 0;
@@ -235,7 +235,7 @@
vector_element = XVECEXP (op, 0, i++);
if (GET_CODE (vector_element) != CLOBBER
- || GET_CODE (XEXP (vector_element, 0)) != REG
+ || !REG_P (XEXP (vector_element, 0))
|| REGNO (XEXP (vector_element, 0)) != 11)
return 0;
}
@@ -283,7 +283,7 @@
dest = SET_DEST (vector_element);
src = SET_SRC (vector_element);
- if (GET_CODE (dest) != REG
+ if (!REG_P (dest)
|| GET_MODE (dest) != SImode
|| ! register_is_ok_for_epilogue (dest, SImode)
|| GET_CODE (src) != MEM
@@ -293,7 +293,7 @@
plus = XEXP (src, 0);
if (GET_CODE (plus) != PLUS
- || GET_CODE (XEXP (plus, 0)) != REG
+ || !REG_P (XEXP (plus, 0))
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (plus, 1)))
@@ -310,7 +310,7 @@
(match_code "reg")
{
/* The save/restore routines can only cope with registers 20 - 31. */
- return ((GET_CODE (op) == REG)
+ return ((REG_P (op))
&& (((REGNO (op) >= 20) && REGNO (op) <= 31)));
})
@@ -355,7 +355,7 @@
dest = SET_DEST (vector_element);
src = SET_SRC (vector_element);
- if ( GET_CODE (dest) != REG
+ if ( !REG_P (dest)
|| GET_MODE (dest) != SImode
|| ! register_is_ok_for_epilogue (dest, SImode)
|| GET_CODE (src) != MEM
@@ -365,7 +365,7 @@
plus = XEXP (src, 0);
if ( GET_CODE (plus) != PLUS
- || GET_CODE (XEXP (plus, 0)) != REG
+ || !REG_P (XEXP (plus, 0))
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (plus, 1)))
@@ -421,7 +421,7 @@
if ( GET_CODE (dest) != MEM
|| GET_MODE (dest) != SImode
- || GET_CODE (src) != REG
+ || !REG_P (src)
|| GET_MODE (src) != SImode
|| ! register_is_ok_for_epilogue (src, SImode)
)
@@ -430,7 +430,7 @@
plus = XEXP (dest, 0);
if ( GET_CODE (plus) != PLUS
- || GET_CODE (XEXP (plus, 0)) != REG
+ || !REG_P (XEXP (plus, 0))
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (plus, 1)))
@@ -519,7 +519,7 @@
if (mode != GET_MODE (op) && mode != VOIDmode)
return 0;
- if ((GET_CODE (XEXP (op, 0)) != REG
+ if ((!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM)
|| XEXP (op, 1) != const0_rtx)
return 0;
@@ -559,7 +559,7 @@
if (mode != GET_MODE (op) && mode != VOIDmode)
return 0;
- if ((GET_CODE (XEXP (op, 0)) != REG
+ if ((!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM)
|| XEXP (op, 1) != const0_rtx)
return 0;
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index ea2222cca1d..201bed4bcdb 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -371,7 +371,7 @@ v850_rtx_costs (rtx x, machine_mode mode, int outer_code,
if (TARGET_V850E
&& (mode == SImode || mode == HImode || mode == QImode))
{
- if (GET_CODE (XEXP (x, 1)) == REG)
+ if (REG_P (XEXP (x, 1)))
*total = 4;
else if (CONST_INT_P (XEXP (x, 1)))
{
@@ -676,7 +676,7 @@ v850_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
fprintf (file, "]");
break;
case LO_SUM:
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
{
/* reg,foo */
fprintf (file, "lo(");
@@ -687,7 +687,7 @@ v850_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
}
break;
case PLUS:
- if (GET_CODE (XEXP (addr, 0)) == REG
+ if (REG_P (XEXP (addr, 0))
|| GET_CODE (XEXP (addr, 0)) == SUBREG)
{
/* reg,foo */
@@ -1096,7 +1096,7 @@ ep_memory_operand (rtx op, machine_mode mode, int unsigned_load)
&& INTVAL (op1) >= 0
&& (INTVAL (op1) & mask) == 0)
{
- if (GET_CODE (op0) == REG && REGNO (op0) == EP_REGNUM)
+ if (REG_P (op0) && REGNO (op0) == EP_REGNUM)
return TRUE;
if (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_TDA_P (op0))
@@ -1180,11 +1180,11 @@ Saved %d bytes (%d uses of register %s) in function %s, starting as insn %d, end
{
rtx addr = XEXP (*p_mem, 0);
- if (GET_CODE (addr) == REG && REGNO (addr) == (unsigned) regno)
+ if (REG_P (addr) && REGNO (addr) == (unsigned) regno)
*p_mem = change_address (*p_mem, VOIDmode, *p_ep);
else if (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& REGNO (XEXP (addr, 0)) == (unsigned) regno
&& CONST_INT_P (XEXP (addr, 1))
&& ((INTVAL (XEXP (addr, 1)))
@@ -1302,11 +1302,11 @@ v850_reorg (void)
subregs to make this code simpler. */
if (GET_CODE (dest) == SUBREG
&& (GET_CODE (SUBREG_REG (dest)) == MEM
- || GET_CODE (SUBREG_REG (dest)) == REG))
+ || REG_P (SUBREG_REG (dest))))
alter_subreg (&dest, false);
if (GET_CODE (src) == SUBREG
&& (GET_CODE (SUBREG_REG (src)) == MEM
- || GET_CODE (SUBREG_REG (src)) == REG))
+ || REG_P (SUBREG_REG (src))))
alter_subreg (&src, false);
if (GET_CODE (dest) == MEM && GET_CODE (src) == MEM)
@@ -1341,14 +1341,14 @@ v850_reorg (void)
int regno = -1;
int short_p;
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
{
short_p = TRUE;
regno = REGNO (addr);
}
else if (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& CONST_INT_P (XEXP (addr, 1))
&& ((INTVAL (XEXP (addr, 1)))
< ep_memory_offset (GET_MODE (mem), unsignedp))
@@ -1372,7 +1372,7 @@ v850_reorg (void)
/* Loading up a register in the basic block zaps any savings
for the register */
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int regno;
int endregno;
@@ -2238,7 +2238,7 @@ construct_restore_jr (rtx op)
rtx vector_element = XVECEXP (op, 0, i);
gcc_assert (GET_CODE (vector_element) == SET);
- gcc_assert (GET_CODE (SET_DEST (vector_element)) == REG);
+ gcc_assert (REG_P (SET_DEST (vector_element)));
gcc_assert (register_is_ok_for_epilogue (SET_DEST (vector_element),
SImode));
@@ -2321,7 +2321,7 @@ construct_save_jarl (rtx op)
/* Paranoia. */
gcc_assert (GET_CODE (XVECEXP (op, 0, 0)) == SET);
gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) == PLUS);
- gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)) == REG);
+ gcc_assert (REG_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)));
gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)));
/* Work out how many bytes to push onto the stack after storing the
@@ -2345,7 +2345,7 @@ construct_save_jarl (rtx op)
rtx vector_element = XVECEXP (op, 0, i);
gcc_assert (GET_CODE (vector_element) == SET);
- gcc_assert (GET_CODE (SET_SRC (vector_element)) == REG);
+ gcc_assert (REG_P (SET_SRC (vector_element)));
gcc_assert (register_is_ok_for_epilogue (SET_SRC (vector_element),
SImode));
@@ -2643,7 +2643,7 @@ construct_dispose_instruction (rtx op)
rtx vector_element = XVECEXP (op, 0, i);
gcc_assert (GET_CODE (vector_element) == SET);
- gcc_assert (GET_CODE (SET_DEST (vector_element)) == REG);
+ gcc_assert (REG_P (SET_DEST (vector_element)));
gcc_assert (register_is_ok_for_epilogue (SET_DEST (vector_element),
SImode));
@@ -2765,7 +2765,7 @@ construct_prepare_instruction (rtx op)
continue;
gcc_assert (GET_CODE (vector_element) == SET);
- gcc_assert (GET_CODE (SET_SRC (vector_element)) == REG);
+ gcc_assert (REG_P (SET_SRC (vector_element)));
gcc_assert (register_is_ok_for_epilogue (SET_SRC (vector_element),
SImode));
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
index 167d87ca60b..06c87e4e7d2 100644
--- a/gcc/config/v850/v850.md
+++ b/gcc/config/v850/v850.md
@@ -1171,9 +1171,9 @@
}
else
{
- if (GET_CODE (operands[2]) != REG)
+ if (!REG_P (operands[2]))
operands[2] = copy_to_mode_reg (SImode,operands[2]);
- if (GET_CODE (operands[3]) != REG)
+ if (!REG_P (operands[3]))
operands[3] = copy_to_mode_reg (SImode, operands[3]);
}
})
@@ -1710,7 +1710,7 @@
{
if (which_alternative == 0)
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
return "jarl %0,r31";
if (TARGET_V850E3V5_UP)
@@ -1779,7 +1779,7 @@
{
if (which_alternative == 0)
{
- if (GET_CODE (operands[1]) == REG)
+ if (REG_P (operands[1]))
return "jarl %1, r31";
/* Reload can generate this pattern.... */
@@ -2728,8 +2728,8 @@
"reload_completed
&& TARGET_USE_FPU
&& GET_MODE(operands[0]) == GET_MODE(operands[1])
- && GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM
- && GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM
+ && REG_P (operands[0]) && REGNO (operands[0]) == CC_REGNUM
+ && REG_P (operands[1]) && REGNO (operands[1]) == FCC_REGNUM
&& (GET_MODE(operands[0]) == CC_FPU_LEmode
|| GET_MODE(operands[0]) == CC_FPU_GEmode
|| GET_MODE(operands[0]) == CC_FPU_LTmode
diff --git a/gcc/config/visium/predicates.md b/gcc/config/visium/predicates.md
index 45c976ac7c1..1515abd968c 100644
--- a/gcc/config/visium/predicates.md
+++ b/gcc/config/visium/predicates.md
@@ -50,7 +50,7 @@
if (GET_CODE (op) == SUBREG)
{
op = SUBREG_REG (op);
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return 1;
}
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index 3362843f488..b2bc847b971 100644
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -1193,7 +1193,7 @@ gr5_avoid_hazard (rtx_insn *insn, unsigned int *last_reg, bool *last_insn_call)
dest = XEXP (dest, 0);
dest_reg = REGNO (dest);
- if (GET_CODE (SET_SRC (set)) == REG)
+ if (REG_P (SET_SRC (set)))
{
unsigned int srcreg = REGNO (SET_SRC (set));
@@ -1903,7 +1903,7 @@ visium_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
{
if (GET_CODE (x) == PLUS
&& CONST_INT_P (XEXP (x, 1))
- && GET_CODE (XEXP (x, 0)) == REG && mode != BLKmode)
+ && REG_P (XEXP (x, 0)) && mode != BLKmode)
{
int offset = INTVAL (XEXP (x, 1));
int size = GET_MODE_SIZE (mode);
@@ -1948,7 +1948,7 @@ visium_legitimize_reload_address (rtx x, machine_mode mode, int opnum,
newrtx = tem ? tem : x;
if (GET_CODE (newrtx) == PLUS
&& CONST_INT_P (XEXP (newrtx, 1))
- && GET_CODE (XEXP (newrtx, 0)) == REG
+ && REG_P (XEXP (newrtx, 0))
&& BASE_REGISTER_P (REGNO (XEXP (newrtx, 0))))
{
int offset = INTVAL (XEXP (newrtx, 1));
@@ -2114,20 +2114,20 @@ visium_split_double_move (rtx *operands, machine_mode mode)
bool swap = false;
/* Check register to register with overlap. */
- if (GET_CODE (operands[0]) == REG
- && GET_CODE (operands[1]) == REG
+ if (REG_P (operands[0])
+ && REG_P (operands[1])
&& REGNO (operands[0]) == REGNO (operands[1]) + 1)
swap = true;
/* Check memory to register where the base reg overlaps the destination. */
- if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == MEM)
+ if (REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
{
rtx op = XEXP (operands[1], 0);
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
- if (GET_CODE (op) == REG && REGNO (op) == REGNO (operands[0]))
+ if (REG_P (op) && REGNO (op) == REGNO (operands[0]))
swap = true;
if (GET_CODE (op) == PLUS)
@@ -2135,10 +2135,10 @@ visium_split_double_move (rtx *operands, machine_mode mode)
rtx x = XEXP (op, 0);
rtx y = XEXP (op, 1);
- if (GET_CODE (x) == REG && REGNO (x) == REGNO (operands[0]))
+ if (REG_P (x) && REGNO (x) == REGNO (operands[0]))
swap = true;
- if (GET_CODE (y) == REG && REGNO (y) == REGNO (operands[0]))
+ if (REG_P (y) && REGNO (y) == REGNO (operands[0]))
swap = true;
}
}
@@ -3323,7 +3323,7 @@ visium_print_operand (FILE *file, rtx op, int letter)
case 'r':
/* It's either a register or zero. */
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
fputs (reg_names[REGNO (op)], file);
else
fputs (reg_names[0], file);
@@ -3331,7 +3331,7 @@ visium_print_operand (FILE *file, rtx op, int letter)
case 'f':
/* It's either a FP register or zero. */
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
fputs (reg_names[REGNO (op)], file);
else
fputs (reg_names[FP_FIRST_REGNUM], file);
@@ -4303,9 +4303,9 @@ reg_or_subreg_regno (rtx op)
{
unsigned int regno;
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
{
if (REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
regno = subreg_regno (op);
diff --git a/gcc/config/visium/visium.md b/gcc/config/visium/visium.md
index e146b89d1da..6f5d3ce3a0b 100644
--- a/gcc/config/visium/visium.md
+++ b/gcc/config/visium/visium.md
@@ -2562,7 +2562,7 @@
(clobber (match_dup 3))])]
""
{
- if (GET_CODE (XEXP (operands[0], 0)) != REG)
+ if (!REG_P (XEXP (operands[0], 0)))
XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
if (!operands[2])
@@ -2593,7 +2593,7 @@
(clobber (match_dup 4))])]
""
{
- if (GET_CODE (XEXP (operands[1], 0)) != REG)
+ if (!REG_P (XEXP (operands[1], 0)))
XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
if (!operands[3])
@@ -2624,7 +2624,7 @@
(clobber (match_dup 3))])]
""
{
- if (GET_CODE (XEXP (operands[0], 0)) != REG)
+ if (!REG_P (XEXP (operands[0], 0)))
XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
if (!operands[2])
@@ -2650,7 +2650,7 @@
(clobber (match_dup 4))])]
""
{
- if (GET_CODE (XEXP (operands[1], 0)) != REG)
+ if (!REG_P (XEXP (operands[1], 0)))
XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
if (!operands[3])
diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
index d35c90f4f88..4d62033d810 100644
--- a/gcc/config/xtensa/predicates.md
+++ b/gcc/config/xtensa/predicates.md
@@ -86,7 +86,7 @@
(define_predicate "call_insn_operand"
(match_code "const_int,const,symbol_ref,reg")
{
- if ((GET_CODE (op) == REG)
+ if ((REG_P (op))
&& (op != arg_pointer_rtx)
&& ((REGNO (op) < FRAME_POINTER_REGNUM)
|| (REGNO (op) > LAST_VIRTUAL_REGISTER)))
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index ba983ad3ac9..d5aad718e41 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -469,7 +469,7 @@ xtensa_mask_immediate (HOST_WIDE_INT v)
int
xt_true_regnum (rtx x)
{
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
if (reg_renumber
&& REGNO (x) >= FIRST_PSEUDO_REGISTER
@@ -528,7 +528,7 @@ smalloffset_mem_p (rtx op)
if (GET_CODE (op) == MEM)
{
rtx addr = XEXP (op, 0);
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
return BASE_REG_P (addr, 0);
if (GET_CODE (addr) == PLUS)
{
@@ -742,7 +742,7 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
cmp1 = force_reg (mode, cmp1);
}
}
- else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
+ else if ((!REG_P (cmp1)) && (GET_CODE (cmp1) != SUBREG))
{
cmp1 = force_reg (mode, cmp1);
}
@@ -1119,7 +1119,7 @@ static rtx
fixup_subreg_mem (rtx x)
{
if (GET_CODE (x) == SUBREG
- && GET_CODE (SUBREG_REG (x)) == REG
+ && REG_P (SUBREG_REG (x))
&& REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
{
rtx temp =
@@ -1173,7 +1173,7 @@ xtensa_copy_incoming_a7 (rtx opnd)
gcc_assert (SUBREG_BYTE (reg) == 0);
reg = SUBREG_REG (reg);
}
- if (GET_CODE (reg) != REG
+ if (!REG_P (reg)
|| REGNO (reg) > A7_REG
|| REGNO (reg) + hard_regno_nregs (A7_REG, mode) <= A7_REG)
return opnd;
@@ -1369,7 +1369,7 @@ xtensa_expand_nonlocal_goto (rtx *operands)
/* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
is too big to generate in-line. */
- if (GET_CODE (containing_fp) != REG)
+ if (!REG_P (containing_fp))
containing_fp = force_reg (Pmode, containing_fp);
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
@@ -1835,7 +1835,7 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
addr = SUBREG_REG (addr);
/* Allow base registers. */
- if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
+ if (REG_P (addr) && BASE_REG_P (addr, strict))
return true;
/* Check for "register + offset" addressing. */
@@ -1969,14 +1969,14 @@ xtensa_legitimize_address (rtx x,
rtx plus0 = XEXP (x, 0);
rtx plus1 = XEXP (x, 1);
- if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
+ if (!REG_P (plus0) && REG_P (plus1))
{
plus0 = XEXP (x, 1);
plus1 = XEXP (x, 0);
}
/* Try to split up the offset to use an ADDMI instruction. */
- if (GET_CODE (plus0) == REG
+ if (REG_P (plus0)
&& CONST_INT_P (plus1)
&& !xtensa_mem_offset (INTVAL (plus1), mode)
&& !xtensa_simm8 (INTVAL (plus1))
@@ -2369,7 +2369,7 @@ print_operand (FILE *file, rtx x, int letter)
switch (letter)
{
case 'D':
- if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || GET_CODE (x) == SUBREG)
fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
else
output_operand_lossage ("invalid %%D value");
@@ -2501,7 +2501,7 @@ print_operand (FILE *file, rtx x, int letter)
/* fall through */
default:
- if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || GET_CODE (x) == SUBREG)
fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
else if (GET_CODE (x) == MEM)
output_address (GET_MODE (x), XEXP (x, 0));
@@ -2540,12 +2540,12 @@ print_operand_address (FILE *file, rtx addr)
rtx arg0 = XEXP (addr, 0);
rtx arg1 = XEXP (addr, 1);
- if (GET_CODE (arg0) == REG)
+ if (REG_P (arg0))
{
reg = arg0;
offset = arg1;
}
- else if (GET_CODE (arg1) == REG)
+ else if (REG_P (arg1))
{
reg = arg1;
offset = arg0;
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index d1448a02f20..40af6056024 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -1549,7 +1549,7 @@
""
{
rtx dest = operands[0];
- if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
+ if (!REG_P (dest) || GET_MODE (dest) != Pmode)
operands[0] = copy_to_mode_reg (Pmode, dest);
emit_jump_insn (gen_indirect_jump_internal (dest));
diff --git a/gcc/cse.c b/gcc/cse.c
index 5a6fcf8cbb7..7747986d637 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -1828,7 +1828,7 @@ check_dependence (const_rtx x, rtx exp, machine_mode mode, rtx addr)
static void
invalidate_reg (rtx x, bool clobber_high)
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
/* If X is a register, dependencies on its contents are recorded
through the qty number mechanism. Just change the qty number of
diff --git a/gcc/dse.c b/gcc/dse.c
index 8d7358d02b4..40ef3fb74e3 100644
--- a/gcc/dse.c
+++ b/gcc/dse.c
@@ -1056,7 +1056,7 @@ const_or_frame_p (rtx x)
if (CONSTANT_P (x))
return true;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
/* Note that we have to test for the actual rtx used for the frame
and arg pointers and not just the register number in case we have
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index c7feaba3718..c49f84d621f 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -1475,7 +1475,7 @@ scan_one_insn (rtx_insn *insn)
if (pat_code == USE || pat_code == CLOBBER)
{
rtx x = XEXP (PATTERN (insn), 0);
- if (GET_CODE (x) == REG
+ if (REG_P (x)
&& REGNO (x) >= FIRST_PSEUDO_REGISTER
&& have_regs_of_mode[GET_MODE (x)])
ira_init_register_move_cost_if_necessary (GET_MODE (x));
diff --git a/gcc/ira.c b/gcc/ira.c
index c58daba6e79..ac3493f202f 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -2206,7 +2206,7 @@ ira_bad_reload_regno_1 (int regno, rtx x)
enum reg_class pref;
/* We only deal with pseudo regs. */
- if (! x || GET_CODE (x) != REG)
+ if (! x || !REG_P (x))
return false;
x_regno = REGNO (x);
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index f2584075937..e2a0c0afe3d 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -720,7 +720,7 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
&& x == SUBREG_REG (y))
return true;
- if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
+ if (REG_P (y) && code == SUBREG && REG_P (SUBREG_REG (x))
&& SUBREG_REG (x) == y)
return true;
diff --git a/gcc/mode-switching.c b/gcc/mode-switching.c
index 2ff21a40081..d706e02faf7 100644
--- a/gcc/mode-switching.c
+++ b/gcc/mode-switching.c
@@ -266,7 +266,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
&& EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == 1
&& NONJUMP_INSN_P ((last_insn = BB_END (src_bb)))
&& GET_CODE (PATTERN (last_insn)) == USE
- && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG)
+ && REG_P ((ret_reg = XEXP (PATTERN (last_insn), 0))))
{
int ret_start = REGNO (ret_reg);
int nregs = REG_NREGS (ret_reg);
@@ -302,7 +302,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
case USE:
/* Skip USEs of multiple return registers.
__builtin_apply pattern is also handled here. */
- if (GET_CODE (XEXP (return_copy_pat, 0)) == REG
+ if (REG_P (XEXP (return_copy_pat, 0))
&& (targetm.calls.function_value_regno_p
(REGNO (XEXP (return_copy_pat, 0)))))
{
@@ -344,7 +344,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
the previous insn is the clobber for
the return register. */
copy_reg = SET_DEST (return_copy_pat);
- if (GET_CODE (copy_reg) == REG
+ if (REG_P (copy_reg)
&& !HARD_REGISTER_NUM_P (REGNO (copy_reg)))
{
if (INSN_P (PREV_INSN (return_copy)))
@@ -358,10 +358,10 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
}
}
copy_reg = SET_DEST (return_copy_pat);
- if (GET_CODE (copy_reg) == REG)
+ if (REG_P (copy_reg))
copy_start = REGNO (copy_reg);
else if (GET_CODE (copy_reg) == SUBREG
- && GET_CODE (SUBREG_REG (copy_reg)) == REG)
+ && REG_P (SUBREG_REG (copy_reg)))
copy_start = REGNO (SUBREG_REG (copy_reg));
else
{
diff --git a/gcc/read-rtl-function.c b/gcc/read-rtl-function.c
index f41f54a0d4a..25d9f674612 100644
--- a/gcc/read-rtl-function.c
+++ b/gcc/read-rtl-function.c
@@ -1446,7 +1446,7 @@ ensure_regno (int regno)
static rtx
consolidate_reg (rtx x)
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
unsigned int regno = REGNO (x);
@@ -1463,7 +1463,7 @@ consolidate_reg (rtx x)
if (regno_reg_rtx[regno] == NULL)
regno_reg_rtx[regno] = x;
/* Use it. */
- gcc_assert (GET_CODE (regno_reg_rtx[regno]) == REG);
+ gcc_assert (REG_P (regno_reg_rtx[regno]));
gcc_assert (REGNO (regno_reg_rtx[regno]) == regno);
if (GET_MODE (x) == GET_MODE (regno_reg_rtx[regno]))
return regno_reg_rtx[regno];
diff --git a/gcc/ree.c b/gcc/ree.c
index 03d610137f9..e4de9743e4c 100644
--- a/gcc/ree.c
+++ b/gcc/ree.c
@@ -541,10 +541,10 @@ is_cond_copy_insn (rtx_insn *insn, rtx *reg1, rtx *reg2)
if (expr != NULL_RTX
&& GET_CODE (expr) == SET
- && GET_CODE (SET_DEST (expr)) == REG
+ && REG_P (SET_DEST (expr))
&& GET_CODE (SET_SRC (expr)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (expr), 1)) == REG
- && GET_CODE (XEXP (SET_SRC (expr), 2)) == REG)
+ && REG_P (XEXP (SET_SRC (expr), 1))
+ && REG_P (XEXP (SET_SRC (expr), 2)))
{
*reg1 = XEXP (SET_SRC (expr), 1);
*reg2 = XEXP (SET_SRC (expr), 2);
diff --git a/gcc/regrename.c b/gcc/regrename.c
index 73c0ceda341..3b144f5e38b 100644
--- a/gcc/regrename.c
+++ b/gcc/regrename.c
@@ -1088,8 +1088,8 @@ scan_rtx_reg (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions act
a single output. */
if (recog_data.n_operands == 2
&& GET_CODE (pat) == SET
- && GET_CODE (SET_DEST (pat)) == REG
- && GET_CODE (SET_SRC (pat)) == REG
+ && REG_P (SET_DEST (pat))
+ && REG_P (SET_SRC (pat))
&& terminated_this_insn
&& terminated_this_insn->nregs
== REG_NREGS (recog_data.operand[1]))
diff --git a/gcc/valtrack.c b/gcc/valtrack.c
index 1f67378a867..87879b5f0f9 100644
--- a/gcc/valtrack.c
+++ b/gcc/valtrack.c
@@ -320,7 +320,7 @@ dead_debug_global_replace_temp (struct dead_debug_global *global,
dead_debug_global_entry *entry
= dead_debug_global_find (global, *DF_REF_REAL_LOC (use));
- gcc_checking_assert (GET_CODE (entry->reg) == REG
+ gcc_checking_assert (REG_P (entry->reg)
&& REGNO (entry->reg) == uregno);
if (!entry->dtemp)
@@ -420,7 +420,7 @@ dead_debug_promote_uses (struct dead_debug_local *debug)
df_ref ref;
dead_debug_global_entry *entry;
- if (GET_CODE (reg) != REG
+ if (!REG_P (reg)
|| REGNO (reg) < FIRST_PSEUDO_REGISTER)
{
headp = &head->next;
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 599c6bd7f33..353df6b6618 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -2609,7 +2609,7 @@ val_reset (dataflow_set *set, decl_or_value dv)
{
if (node->loc == cval)
continue;
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
var_reg_decl_set (set, node->loc, node->init, cdv, 0,
node->set_src, NO_INSERT);
else if (GET_CODE (node->loc) == MEM)
@@ -3814,7 +3814,7 @@ canonicalize_values_star (variable **slot, dataflow_set *set)
parent. */
clobber_variable_part (set, cval, ndv, 0, NULL);
}
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
{
attrs *list = set->regs[REGNO (node->loc)], **listp;
@@ -4072,7 +4072,7 @@ variable_merge_over_cur (variable *s1var, struct dfset_merge *dsm)
{
location_chain **nextp = &node->next;
- if (GET_CODE (node->loc) == REG)
+ if (REG_P (node->loc))
{
attrs *list;
@@ -4444,7 +4444,7 @@ variable_post_merge_new_vals (variable **slot, dfset_post_merge *dfpm)
{
if (GET_CODE (node->loc) == VALUE)
gcc_assert (!VALUE_RECURSED_INTO (node->loc));
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
{
attrs *att, **attp, **curp = NULL;
@@ -6832,7 +6832,7 @@ compute_bb_dataflow (basic_block bb)
if (VAL_HOLDS_TRACK_EXPR (loc))
{
- if (GET_CODE (uloc) == REG)
+ if (REG_P (uloc))
var_reg_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
else if (GET_CODE (uloc) == MEM)
@@ -6885,7 +6885,7 @@ compute_bb_dataflow (basic_block bb)
else if (VAL_NEEDS_RESOLUTION (loc))
{
gcc_assert (GET_CODE (uloc) == SET
- && GET_CODE (SET_SRC (uloc)) == REG);
+ && REG_P (SET_SRC (uloc)));
val_resolve (out, val, SET_SRC (uloc), insn);
}
@@ -9330,7 +9330,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
if (VAL_HOLDS_TRACK_EXPR (loc))
{
- if (GET_CODE (uloc) == REG)
+ if (REG_P (uloc))
var_reg_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
else if (GET_CODE (uloc) == MEM)
@@ -9385,7 +9385,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
else if (VAL_NEEDS_RESOLUTION (loc))
{
gcc_assert (GET_CODE (uloc) == SET
- && GET_CODE (SET_SRC (uloc)) == REG);
+ && REG_P (SET_SRC (uloc)));
val_resolve (set, val, SET_SRC (uloc), insn);
}
--
2.21.0