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[PATCH v2 12/18] Use SUBREG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh SUBREG
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* bt-load.c: Convert GET_CODE (..) == SUBREG to SUBREG_P (..).
* caller-save.c: Likewise.
* calls.c: Likewise.
* cfgexpand.c: Likewise.
* combine.c: Likewise.
* config/aarch64/aarch64.c: Likewise.
* config/arc/arc.c: Likewise.
* config/arm/aarch-common.c: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/arm.h: Likewise.
* config/arm/arm.md: Likewise.
* config/arm/predicates.md: Likewise.
* config/bfin/bfin.c: Likewise.
* config/bfin/predicates.md: Likewise.
* config/c6x/c6x.c: Likewise.
* config/c6x/c6x.md: Likewise.
* config/cr16/cr16.c: Likewise.
* config/cris/cris.c: Likewise.
* config/cris/cris.h: Likewise.
* config/csky/csky.c: Likewise.
* config/darwin.c: Likewise.
* config/epiphany/epiphany.md: Likewise.
* config/epiphany/predicates.md: Likewise.
* config/fr30/fr30.md: Likewise.
* config/fr30/predicates.md: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/predicates.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/gcn/predicates.md: Likewise.
* config/h8300/h8300.c: Likewise.
* config/h8300/h8300.md: Likewise.
* config/h8300/predicates.md: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/predicates.md: Likewise.
* config/iq2000/iq2000.c: Likewise.
* config/lm32/lm32.md: Likewise.
* config/m32c/m32c.c: Likewise.
* config/m32r/m32r.c: Likewise.
* config/m32r/m32r.md: Likewise.
* config/m32r/predicates.md: Likewise.
* config/m68k/m68k.c: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mcore/mcore.md: Likewise.
* config/mcore/predicates.md: Likewise.
* config/microblaze/microblaze.c: Likewise.
* config/mips/mips.c: Likewise.
* config/mn10300/mn10300.c: Likewise.
* config/mn10300/mn10300.h: Likewise.
* config/msp430/msp430.c: Likewise.
* config/msp430/msp430.md: Likewise.
* config/nds32/nds32-pipelines-auxiliary.c: Likewise.
* config/nds32/nds32-utils.c: Likewise.
* config/nds32/nds32.md: Likewise.
* config/nds32/predicates.md: Likewise.
* config/nios2/nios2.c: Likewise.
* config/nvptx/nvptx.c: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/predicates.md: Likewise.
* config/pru/predicates.md: Likewise.
* config/pru/pru.c: Likewise.
* config/riscv/riscv.c: Likewise.
* config/rl78/rl78-expand.md: Likewise.
* config/rl78/rl78.c: Likewise.
* config/rl78/rl78.h: Likewise.
* config/rx/rx.h: Likewise.
* config/s390/predicates.md: Likewise.
* config/s390/s390.c: Likewise.
* config/sh/predicates.md: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.h: Likewise.
* config/sh/sh.md: Likewise.
* config/sparc/predicates.md: Likewise.
* config/sparc/sparc.c: Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/spu.c: Likewise.
* config/stormy16/predicates.md: Likewise.
* config/stormy16/stormy16.c: Likewise.
* config/tilegx/tilegx.c: Likewise.
* config/tilepro/tilepro.c: Likewise.
* config/v850/v850.c: Likewise.
* config/visium/predicates.md: Likewise.
* config/visium/visium.c: Likewise.
* config/xtensa/xtensa.c: Likewise.
* config/xtensa/xtensa.md: Likewise.
* cse.c: Likewise.
* cselib.c: Likewise.
* dbxout.c: Likewise.
* df-core.c: Likewise.
* df-problems.c: Likewise.
* df-scan.c: Likewise.
* df.h: Likewise.
* dojump.c: Likewise.
* dse.c: Likewise.
* dwarf2out.c: Likewise.
* emit-rtl.c: Likewise.
* expmed.c: Likewise.
* expr.c: Likewise.
* final.c: Likewise.
* function.c: Likewise.
* fwprop.c: Likewise.
* gcse-common.c: Likewise.
* gcse.c: Likewise.
* genpreds.c: Likewise.
* ifcvt.c: Likewise.
* internal-fn.c: Likewise.
* ira-build.c: Likewise.
* ira-conflicts.c: Likewise.
* ira-costs.c: Likewise.
* ira-emit.c: Likewise.
* ira-lives.c: Likewise.
* ira.c: Likewise.
* jump.c: Likewise.
* loop-invariant.c: Likewise.
* loop-iv.c: Likewise.
* loop-unroll.c: Likewise.
* lower-subreg.c: Likewise.
* lra-constraints.c: Likewise.
* lra-eliminations.c: Likewise.
* lra.c: Likewise.
* mode-switching.c: Likewise.
* modulo-sched.c: Likewise.
* optabs.c: Likewise.
* postreload-gcse.c: Likewise.
* postreload.c: Likewise.
* read-rtl.c: Likewise.
* recog.c: Likewise.
* ree.c: Likewise.
* reg-stack.c: Likewise.
* regcprop.c: Likewise.
* reginfo.c: Likewise.
* regrename.c: Likewise.
* reload.c: Likewise.
* reload1.c: Likewise.
* resource.c: Likewise.
* rtlanal.c: Likewise.
* rtlhooks.c: Likewise.
* sched-deps.c: Likewise.
* sched-rgn.c: Likewise.
* sel-sched.c: Likewise.
* simplify-rtx.c: Likewise.
* valtrack.c: Likewise.
* var-tracking.c: Likewise.
142 files changed, 735 insertions(+), 735 deletions(-)
diff --git a/gcc/bt-load.c b/gcc/bt-load.c
index f68879ca49a..11eee41e9d5 100644
--- a/gcc/bt-load.c
+++ b/gcc/bt-load.c
@@ -226,7 +226,7 @@ insn_sets_btr_p (const rtx_insn *insn, int check_const, int *regno)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = XEXP (dest, 0);
if (REG_P (dest)
diff --git a/gcc/caller-save.c b/gcc/caller-save.c
index 7c1de894976..e816d080b82 100644
--- a/gcc/caller-save.c
+++ b/gcc/caller-save.c
@@ -955,7 +955,7 @@ mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data)
int regno, endregno, i;
HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
rtx inner = SUBREG_REG (reg);
if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER)
@@ -990,7 +990,7 @@ add_stored_regs (rtx reg, const_rtx setter, void *data)
if (GET_CODE (setter) == CLOBBER)
return;
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& REG_P (SUBREG_REG (reg))
&& REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER)
{
diff --git a/gcc/calls.c b/gcc/calls.c
index 7507b698e27..453308f1ca1 100644
--- a/gcc/calls.c
+++ b/gcc/calls.c
@@ -1004,7 +1004,7 @@ precompute_register_parameters (int num_actuals, struct arg_data *args,
loading the parameters registers. */
else if ((! (REG_P (args[i].value)
- || (GET_CODE (args[i].value) == SUBREG
+ || (SUBREG_P (args[i].value)
&& REG_P (SUBREG_REG (args[i].value)))))
&& args[i].mode != BLKmode
&& (set_src_cost (args[i].value, args[i].mode,
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index b141a57d3af..aff97bb41be 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -3786,7 +3786,7 @@ expand_gimple_stmt_1 (gimple *stmt)
bool promoted = false;
target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
- if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
promoted = true;
ops.code = gimple_assign_rhs_code (assign_stmt);
diff --git a/gcc/combine.c b/gcc/combine.c
index 1c59ab54a40..b175ed9c4a0 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -582,7 +582,7 @@ find_single_use_1 (rtx dest, rtx *loc)
if (GET_CODE (SET_DEST (x)) != CC0
&& GET_CODE (SET_DEST (x)) != PC
&& !REG_P (SET_DEST (x))
- && ! (GET_CODE (SET_DEST (x)) == SUBREG
+ && ! (SUBREG_P (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& !read_modify_subreg_p (SET_DEST (x))))
break;
@@ -738,7 +738,7 @@ do_SUBST (rtx *into, rtx newval)
when do_SUBST is called to replace the operand thereof, so we
perform this test on oldval instead, checking whether an
invalid replacement took place before we got here. */
- gcc_assert (!(GET_CODE (oldval) == SUBREG
+ gcc_assert (!(SUBREG_P (oldval)
&& CONST_INT_P (SUBREG_REG (oldval))));
gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
&& CONST_INT_P (XEXP (oldval, 0))));
@@ -2222,7 +2222,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
rtx subdest;
while (GET_CODE (inner_dest) == STRICT_LOW_PART
- || GET_CODE (inner_dest) == SUBREG
+ || SUBREG_P (inner_dest)
|| GET_CODE (inner_dest) == ZERO_EXTRACT)
inner_dest = XEXP (inner_dest, 0);
@@ -2265,7 +2265,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
STACK_POINTER_REGNUM, since these are always considered to be
live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
subdest = dest;
- if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
+ if (SUBREG_P (subdest) && !partial_subreg_p (subdest))
subdest = SUBREG_REG (subdest);
if (pi3dest_killed
&& REG_P (subdest)
@@ -2352,9 +2352,9 @@ cant_combine_insn_p (rtx_insn *insn)
return 0;
src = SET_SRC (set);
dest = SET_DEST (set);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
src = SUBREG_REG (src);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (src) && REG_P (dest)
&& ((HARD_REGISTER_P (src)
@@ -2476,7 +2476,7 @@ adjust_for_new_dest (rtx_insn *insn)
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
gcc_assert (REG_P (reg));
@@ -2530,7 +2530,7 @@ reg_subword_p (rtx x, rtx reg)
|| GET_CODE (x) == ZERO_EXTRACT)
x = XEXP (x, 0);
- return GET_CODE (x) == SUBREG
+ return SUBREG_P (x)
&& SUBREG_REG (x) == reg
&& GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
}
@@ -3625,7 +3625,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if (((REG_P (SET_DEST (set1))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
- || (GET_CODE (SET_DEST (set1)) == SUBREG
+ || (SUBREG_P (SET_DEST (set1))
&& find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
&& insn_nothrow_p (i3)
&& !side_effects_p (SET_SRC (set1)))
@@ -3636,14 +3636,14 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
else if (((REG_P (SET_DEST (set0))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
- || (GET_CODE (SET_DEST (set0)) == SUBREG
+ || (SUBREG_P (SET_DEST (set0))
&& find_reg_note (i3, REG_UNUSED,
SUBREG_REG (SET_DEST (set0)))))
&& insn_nothrow_p (i3)
&& !side_effects_p (SET_SRC (set0)))
{
rtx dest = SET_DEST (set1);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (!reg_used_between_p (dest, i2, i3))
{
@@ -3800,12 +3800,12 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
|| GET_CODE (new_i3_dest) == STRICT_LOW_PART
- || GET_CODE (new_i3_dest) == SUBREG)
+ || SUBREG_P (new_i3_dest))
new_i3_dest = XEXP (new_i3_dest, 0);
while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
|| GET_CODE (new_i2_dest) == STRICT_LOW_PART
- || GET_CODE (new_i2_dest) == SUBREG)
+ || SUBREG_P (new_i2_dest))
new_i2_dest = XEXP (new_i2_dest, 0);
if (REG_P (new_i3_dest)
@@ -4037,7 +4037,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
HOST_BITS_PER_INT)
&& (reg_stat[REGNO (temp_expr)].nonzero_bits
!= GET_MODE_MASK (word_mode))))
- && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
+ && ! (SUBREG_P (SET_DEST (XVECEXP (newpat, 0, 1)))
&& (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
(REG_P (temp_expr)
&& reg_stat[REGNO (temp_expr)].nonzero_bits != 0
@@ -4112,7 +4112,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if (!modified_between_p (SET_SRC (set1), i2, i3)
&& !(REG_P (SET_DEST (set1))
&& find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
- && !(GET_CODE (SET_DEST (set1)) == SUBREG
+ && !(SUBREG_P (SET_DEST (set1))
&& find_reg_note (i2, REG_DEAD,
SUBREG_REG (SET_DEST (set1))))
&& !modified_between_p (SET_DEST (set1), i2, i3)
@@ -4128,7 +4128,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
else if (!modified_between_p (SET_SRC (set0), i2, i3)
&& !(REG_P (SET_DEST (set0))
&& find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
- && !(GET_CODE (SET_DEST (set0)) == SUBREG
+ && !(SUBREG_P (SET_DEST (set0))
&& find_reg_note (i2, REG_DEAD,
SUBREG_REG (SET_DEST (set0))))
&& !modified_between_p (SET_DEST (set0), i2, i3)
@@ -5045,7 +5045,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
- && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
0), 0)))))
{
@@ -5062,7 +5062,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
- && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
0), 1)))))
{
@@ -5082,7 +5082,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
This will occur on machines that just support REG + CONST
and have a constant moved through some previous computation. */
if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
- && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (x, 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
return &XEXP (XEXP (x, 0), 0);
}
@@ -5093,7 +5093,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
&& ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
MEM_ADDR_SPACE (x))
&& ! OBJECT_P (XEXP (XEXP (x, 0), 0))
- && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (x, 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
return &XEXP (XEXP (x, 0), 0);
break;
@@ -5108,7 +5108,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
&& GET_CODE (SET_SRC (x)) != COMPARE
&& GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
&& !OBJECT_P (SET_SRC (x))
- && ! (GET_CODE (SET_SRC (x)) == SUBREG
+ && ! (SUBREG_P (SET_SRC (x))
&& OBJECT_P (SUBREG_REG (SET_SRC (x)))))
return &SET_SRC (x);
@@ -5313,7 +5313,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (BINARY_P (SET_SRC (x))
&& CONSTANT_P (XEXP (SET_SRC (x), 1))
&& (OBJECT_P (XEXP (SET_SRC (x), 0))
- || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
+ || (SUBREG_P (XEXP (SET_SRC (x), 0))
&& OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
return &XEXP (SET_SRC (x), 1);
@@ -5626,7 +5626,7 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
tieable and it is valid if X is a SET that copies
FROM to CC0. */
- if (GET_CODE (to) == SUBREG
+ if (SUBREG_P (to)
&& !targetm.modes_tieable_p (GET_MODE (to),
GET_MODE (SUBREG_REG (to)))
&& ! (code == SUBREG
@@ -5676,7 +5676,7 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
return new_rtx;
- if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
+ if (SUBREG_P (x) && CONST_SCALAR_INT_P (new_rtx))
{
machine_mode mode = GET_MODE (x);
@@ -5830,14 +5830,14 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
if ((BINARY_P (x)
&& ((!OBJECT_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
|| (!OBJECT_P (XEXP (x, 1))
- && ! (GET_CODE (XEXP (x, 1)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 1))
&& OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
|| (UNARY_P (x)
&& (!OBJECT_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
{
rtx cond, true_rtx, false_rtx;
@@ -6049,7 +6049,7 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
complex if it was just a register. */
if (!REG_P (temp)
- && ! (GET_CODE (temp) == SUBREG
+ && ! (SUBREG_P (temp)
&& REG_P (SUBREG_REG (temp)))
&& is_a <scalar_int_mode> (mode, &int_mode)
&& (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
@@ -6151,7 +6151,7 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
"a = (b & 8) == 0;" */
if (XEXP (x, 1) == constm1_rtx
&& !REG_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& REG_P (SUBREG_REG (XEXP (x, 0))))
&& is_a <scalar_int_mode> (mode, &int_mode)
&& nonzero_bits (XEXP (x, 0), int_mode) == 1)
@@ -6587,7 +6587,7 @@ simplify_if_then_else (rtx x)
&& !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
|| true_rtx == const0_rtx
|| (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
- || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
+ || (SUBREG_P (true_rtx) && OBJECT_P (SUBREG_REG (true_rtx))
&& !OBJECT_P (false_rtx))
|| reg_mentioned_p (true_rtx, false_rtx)
|| rtx_equal_p (false_rtx, XEXP (cond, 0))))
@@ -6712,7 +6712,7 @@ simplify_if_then_else (rtx x)
|| GET_CODE (XEXP (t, 0)) == ASHIFT
|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
- && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 0))
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
&& (num_sign_bit_copies (f, GET_MODE (f))
@@ -6729,7 +6729,7 @@ simplify_if_then_else (rtx x)
&& (GET_CODE (XEXP (t, 0)) == PLUS
|| GET_CODE (XEXP (t, 0)) == IOR
|| GET_CODE (XEXP (t, 0)) == XOR)
- && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 1))
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
&& (num_sign_bit_copies (f, GET_MODE (f))
@@ -6750,7 +6750,7 @@ simplify_if_then_else (rtx x)
|| GET_CODE (XEXP (t, 0)) == ASHIFT
|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
- && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 0))
&& HWI_COMPUTABLE_MODE_P (int_mode)
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
@@ -6767,7 +6767,7 @@ simplify_if_then_else (rtx x)
&& (GET_CODE (XEXP (t, 0)) == PLUS
|| GET_CODE (XEXP (t, 0)) == IOR
|| GET_CODE (XEXP (t, 0)) == XOR)
- && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 1))
&& HWI_COMPUTABLE_MODE_P (int_mode)
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
@@ -7051,7 +7051,7 @@ simplify_set (rtx x)
be undefined. On machine where it is defined, this transformation is safe
as long as M1 and M2 have the same number of words. */
- if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
+ if (SUBREG_P (src) && subreg_lowpart_p (src)
&& !OBJECT_P (SUBREG_REG (src))
&& (known_equal_after_align_up
(GET_MODE_SIZE (GET_MODE (src)),
@@ -7063,7 +7063,7 @@ simplify_set (rtx x)
GET_MODE (SUBREG_REG (src)),
GET_MODE (src)))
&& (REG_P (dest)
- || (GET_CODE (dest) == SUBREG
+ || (SUBREG_P (dest)
&& REG_P (SUBREG_REG (dest)))))
{
SUBST (SET_DEST (x),
@@ -7387,7 +7387,7 @@ expand_compound_operation (rtx x)
return XEXP (XEXP (x, 0), 0);
/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
+ if (SUBREG_P (XEXP (x, 0))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
&& subreg_lowpart_p (XEXP (x, 0))
&& HWI_COMPUTABLE_MODE_P (mode)
@@ -7407,7 +7407,7 @@ expand_compound_operation (rtx x)
return XEXP (XEXP (x, 0), 0);
/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
+ if (SUBREG_P (XEXP (x, 0))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
&& subreg_lowpart_p (XEXP (x, 0))
&& COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
@@ -7482,7 +7482,7 @@ expand_field_assignment (const_rtx x)
while (1)
{
if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
- && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
+ && SUBREG_P (XEXP (SET_DEST (x), 0)))
{
rtx x0 = XEXP (SET_DEST (x), 0);
if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
@@ -7524,7 +7524,7 @@ expand_field_assignment (const_rtx x)
/* If the destination is a subreg that overwrites the whole of the inner
register, we can move the subreg to the source. */
- else if (GET_CODE (SET_DEST (x)) == SUBREG
+ else if (SUBREG_P (SET_DEST (x))
/* We need SUBREGs to compute nonzero_bits properly. */
&& nonzero_sign_valid
&& !read_modify_subreg_p (SET_DEST (x)))
@@ -7538,7 +7538,7 @@ expand_field_assignment (const_rtx x)
else
break;
- while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
+ while (SUBREG_P (inner) && subreg_lowpart_p (inner))
inner = SUBREG_REG (inner);
/* Don't attempt bitwise arithmetic on non scalar integer modes. */
@@ -7631,7 +7631,7 @@ make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
if (pos_rtx && CONST_INT_P (pos_rtx))
pos = INTVAL (pos_rtx), pos_rtx = 0;
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& subreg_lowpart_p (inner)
&& (paradoxical_subreg_p (inner)
/* If trying or potentionally trying to extract
@@ -7764,7 +7764,7 @@ make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
if (in_dest)
return (MEM_P (new_rtx) ? new_rtx
- : (GET_CODE (new_rtx) != SUBREG
+ : (!SUBREG_P (new_rtx)
? gen_rtx_CLOBBER (tmode, const0_rtx)
: gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
@@ -8189,7 +8189,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
}
/* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
- else if (GET_CODE (XEXP (x, 0)) == SUBREG
+ else if (SUBREG_P (XEXP (x, 0))
&& subreg_lowpart_p (XEXP (x, 0))
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
&inner_mode)
@@ -8294,7 +8294,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
the constant (limited to the smaller mode) has only zero bits where
the sub expression has known zero bits, this can be expressed as
a zero_extend. */
- else if (GET_CODE (XEXP (x, 0)) == SUBREG)
+ else if (SUBREG_P (XEXP (x, 0)))
{
rtx sub;
@@ -8365,7 +8365,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
seem worth the effort; the case checked for occurs on Alpha. */
if (!OBJECT_P (lhs)
- && ! (GET_CODE (lhs) == SUBREG
+ && ! (SUBREG_P (lhs)
&& (OBJECT_P (SUBREG_REG (lhs))))
&& CONST_INT_P (rhs)
&& INTVAL (rhs) >= 0
@@ -8410,7 +8410,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
to the recursive make_compound_operation call. */
if (subreg_code == COMPARE
&& (!subreg_lowpart_p (x)
- || GET_CODE (inner) == SUBREG
+ || SUBREG_P (inner)
/* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
is (const_int 0), rather than
(subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
@@ -8440,7 +8440,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
/* If we have something other than a SUBREG, we might have
done an expansion, so rerun ourselves. */
- if (GET_CODE (newer) != SUBREG)
+ if (!SUBREG_P (newer))
newer = make_compound_operation (newer, in_code);
/* force_to_mode can expand compounds. If it just re-expanded
@@ -8450,7 +8450,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
/* Likewise if it re-expanded the compound only partially.
This happens for SUBREG of ZERO_EXTRACT if they extract
the same number of bits. */
- || (GET_CODE (newer) == SUBREG
+ || (SUBREG_P (newer)
&& (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
|| GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
&& GET_CODE (inner) == AND
@@ -8777,7 +8777,7 @@ force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
/* We can ignore the effect of a SUBREG if it narrows the mode or
if the constant masks to zero all the bits the mode doesn't have. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& subreg_lowpart_p (x)
&& (partial_subreg_p (x)
|| (mask
@@ -9711,13 +9711,13 @@ rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
/* Check for a paradoxical SUBREG of a MEM compared with the MEM.
Note that all SUBREGs of MEM are paradoxical; otherwise they
would have been rewritten. */
- if (MEM_P (x) && GET_CODE (y) == SUBREG
+ if (MEM_P (x) && SUBREG_P (y)
&& MEM_P (SUBREG_REG (y))
&& rtx_equal_p (SUBREG_REG (y),
gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
return 1;
- if (MEM_P (y) && GET_CODE (x) == SUBREG
+ if (MEM_P (y) && SUBREG_P (x)
&& MEM_P (SUBREG_REG (x))
&& rtx_equal_p (SUBREG_REG (x),
gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
@@ -9770,7 +9770,7 @@ make_field_assignment (rtx x)
return x;
}
- if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
+ if (GET_CODE (src) == AND && SUBREG_P (XEXP (src, 0))
&& subreg_lowpart_p (XEXP (src, 0))
&& partial_subreg_p (XEXP (src, 0))
&& GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
@@ -9842,7 +9842,7 @@ make_field_assignment (rtx x)
narrowing SUBREG, which we can just strip for the purposes of
identifying the constant-field assignment. */
scalar_int_mode src_mode = mode;
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& subreg_lowpart_p (src)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
src = SUBREG_REG (src);
@@ -11622,7 +11622,7 @@ change_zero_ext (rtx pat)
}
}
else if (GET_CODE (x) == ZERO_EXTEND
- && GET_CODE (XEXP (x, 0)) == SUBREG
+ && SUBREG_P (XEXP (x, 0))
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
&& !paradoxical_subreg_p (XEXP (x, 0))
&& subreg_lowpart_p (XEXP (x, 0)))
@@ -11781,7 +11781,7 @@ gen_lowpart_for_combine (machine_mode omode, rtx x)
/* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
won't know what to do. So we will strip off the SUBREG here and
process normally. */
- if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
+ if (SUBREG_P (x) && MEM_P (SUBREG_REG (x)))
{
x = SUBREG_REG (x);
@@ -12076,8 +12076,8 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
&& GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
&& GET_CODE (XEXP (op0, 0)) == ASHIFT
&& GET_CODE (XEXP (op1, 0)) == ASHIFT
- && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
- && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (op0, 0), 0))
+ && SUBREG_P (XEXP (XEXP (op1, 0), 0))
&& is_a <scalar_int_mode> (GET_MODE (op0), &mode)
&& (is_a <scalar_int_mode>
(GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
@@ -12151,7 +12151,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
int changed = 0;
if (paradoxical_subreg_p (inner_op0)
- && GET_CODE (inner_op1) == SUBREG
+ && SUBREG_P (inner_op1)
&& HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
&& (GET_MODE (SUBREG_REG (inner_op0))
== GET_MODE (SUBREG_REG (inner_op1)))
@@ -12729,7 +12729,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
fits in both M1 and M2 and the SUBREG is either paradoxical
or represents the low part, permute the SUBREG and the AND
and try again. */
- if (GET_CODE (XEXP (op0, 0)) == SUBREG
+ if (SUBREG_P (XEXP (op0, 0))
&& CONST_INT_P (XEXP (op0, 1)))
{
unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
@@ -13008,7 +13008,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
op0 = make_compound_operation (op0, op0_mco_code);
op1 = make_compound_operation (op1, SET);
- if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
+ if (SUBREG_P (op0) && subreg_lowpart_p (op0)
&& is_int_mode (GET_MODE (op0), &mode)
&& is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
&& (code == NE || code == EQ))
@@ -13376,7 +13376,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
{
rtx_insn *record_dead_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (!record_dead_insn)
@@ -13397,7 +13397,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
else if (GET_CODE (setter) == SET
- && GET_CODE (SET_DEST (setter)) == SUBREG
+ && SUBREG_P (SET_DEST (setter))
&& SUBREG_REG (SET_DEST (setter)) == dest
&& known_le (GET_MODE_PRECISION (GET_MODE (dest)),
BITS_PER_WORD)
@@ -13577,7 +13577,7 @@ record_truncated_value (rtx x)
machine_mode truncated_mode;
reg_stat_type *rsp;
- if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
+ if (SUBREG_P (x) && REG_P (SUBREG_REG (x)))
{
machine_mode original_mode = GET_MODE (SUBREG_REG (x));
truncated_mode = GET_MODE (x);
@@ -13629,7 +13629,7 @@ record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
static void
check_promoted_subreg (rtx_insn *insn, rtx x)
{
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_PROMOTED_VAR_P (x)
&& REG_P (SUBREG_REG (x)))
record_promoted_value (insn, x);
@@ -13775,7 +13775,7 @@ get_last_value (const_rtx x)
/* If this is a non-paradoxical SUBREG, get the value of its operand and
then convert it to the desired mode. If this is a paradoxical SUBREG,
we cannot predict what values the "extra" bits might have. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& subreg_lowpart_p (x)
&& !paradoxical_subreg_p (x)
&& (value = get_last_value (SUBREG_REG (x))) != 0)
@@ -13982,7 +13982,7 @@ mark_used_regs_combine (rtx x)
the address. */
rtx testreg = SET_DEST (x);
- while (GET_CODE (testreg) == SUBREG
+ while (SUBREG_P (testreg)
|| GET_CODE (testreg) == ZERO_EXTRACT
|| GET_CODE (testreg) == STRICT_LOW_PART)
testreg = XEXP (testreg, 0);
@@ -14162,7 +14162,7 @@ move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
if (GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART
- || (GET_CODE (dest) == SUBREG
+ || (SUBREG_P (dest)
&& !read_modify_subreg_p (dest)))
{
move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
@@ -14171,7 +14171,7 @@ move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
/* If this is some other SUBREG, we know it replaces the entire
value, so use that as the destination. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
/* If this is a MEM, adjust deaths of anything used in the address.
@@ -14225,7 +14225,7 @@ reg_bitfield_target_p (rtx x, rtx body)
else
return 0;
- if (GET_CODE (target) == SUBREG)
+ if (SUBREG_P (target))
target = SUBREG_REG (target);
if (!REG_P (target))
@@ -14624,7 +14624,7 @@ distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
if (set != 0)
for (inner_dest = SET_DEST (set);
(GET_CODE (inner_dest) == STRICT_LOW_PART
- || GET_CODE (inner_dest) == SUBREG
+ || SUBREG_P (inner_dest)
|| GET_CODE (inner_dest) == ZERO_EXTRACT);
inner_dest = XEXP (inner_dest, 0))
;
@@ -14892,7 +14892,7 @@ distribute_links (struct insn_link *links)
reg = SET_DEST (set);
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
if (!REG_P (reg))
@@ -14911,7 +14911,7 @@ distribute_links (struct insn_link *links)
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
if (reg == pc_rtx)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 9bdbc198dae..70cac11c257 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3522,9 +3522,9 @@ bool
aarch64_maybe_expand_sve_subreg_move (rtx dest, rtx src)
{
gcc_assert (BYTES_BIG_ENDIAN);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
src = SUBREG_REG (src);
/* The optimization handles two single SVE REGs with different element
@@ -6414,7 +6414,7 @@ static bool
aarch64_base_register_rtx_p (rtx x, bool strict_p)
{
if (!strict_p
- && GET_CODE (x) == SUBREG
+ && SUBREG_P (x)
&& contains_reg_of_mode[GENERAL_REGS][GET_MODE (SUBREG_REG (x))])
x = SUBREG_REG (x);
@@ -6433,7 +6433,7 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x,
int shift;
/* (reg:P) */
- if ((REG_P (x) || GET_CODE (x) == SUBREG)
+ if ((REG_P (x) || SUBREG_P (x))
&& GET_MODE (x) == Pmode)
{
type = ADDRESS_REG_REG;
@@ -6563,7 +6563,7 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x,
return false;
if (!strict_p
- && GET_CODE (index) == SUBREG
+ && SUBREG_P (index)
&& contains_reg_of_mode[GENERAL_REGS][GET_MODE (SUBREG_REG (index))])
index = SUBREG_REG (index);
@@ -7294,7 +7294,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
the comparison will have to be swapped when we emit the assembly
code. */
if ((mode_x == SImode || mode_x == DImode)
- && (REG_P (y) || GET_CODE (y) == SUBREG || y == const0_rtx)
+ && (REG_P (y) || SUBREG_P (y) || y == const0_rtx)
&& (code_x == ASHIFT || code_x == ASHIFTRT
|| code_x == LSHIFTRT
|| code_x == ZERO_EXTEND || code_x == SIGN_EXTEND))
@@ -7303,7 +7303,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
/* Similarly for a negated operand, but we can only do this for
equalities. */
if ((mode_x == SImode || mode_x == DImode)
- && (REG_P (y) || GET_CODE (y) == SUBREG)
+ && (REG_P (y) || SUBREG_P (y))
&& (code == EQ || code == NE)
&& code_x == NEG)
return CC_Zmode;
@@ -8615,7 +8615,7 @@ aarch64_preferred_reload_class (rtx x, reg_class_t regclass)
rtx lhs = XEXP (x, 0);
/* Look through a possible SUBREG introduced by ILP32. */
- if (GET_CODE (lhs) == SUBREG)
+ if (SUBREG_P (lhs))
lhs = SUBREG_REG (lhs);
gcc_assert (REG_P (lhs));
@@ -9523,7 +9523,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
case SIGN_EXTRACT:
/* Bit-field insertion. Strip any redundant widening of
the RHS to meet the width of the target. */
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = SUBREG_REG (op1);
if ((GET_CODE (op1) == ZERO_EXTEND
|| GET_CODE (op1) == SIGN_EXTEND)
@@ -9789,7 +9789,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
But the integer MINUS logic expects the shift/extend
operation in op1. */
if (! (REG_P (op0)
- || (GET_CODE (op0) == SUBREG && REG_P (SUBREG_REG (op0)))))
+ || (SUBREG_P (op0) && REG_P (SUBREG_REG (op0)))))
{
op0 = XEXP (x, 1);
op1 = XEXP (x, 0);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index e417756a9f4..5a06d94d5f7 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -11352,7 +11352,7 @@ mem_ok_for_ldd_std (rtx mem, rtx *base, rtx *offset)
return false;
/* Can't deal with subregs. */
- if (GET_CODE (mem) == SUBREG)
+ if (SUBREG_P (mem))
return false;
gcc_assert (MEM_P (mem));
@@ -11412,7 +11412,7 @@ gen_operands_ldd_std (rtx *operands, bool load, bool commute)
return false;
offsets[i] = INTVAL (cur_offset);
- if (GET_CODE (operands[i]) == SUBREG)
+ if (SUBREG_P (operands[i]))
{
tmp = SUBREG_REG (operands[i]);
gcc_assert (GET_MODE (operands[i]) == GET_MODE (tmp));
diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c
index 965a07a43e3..7348c42be85 100644
--- a/gcc/config/arm/aarch-common.c
+++ b/gcc/config/arm/aarch-common.c
@@ -479,7 +479,7 @@ aarch_accumulator_forwarding (rtx_insn *producer, rtx_insn *consumer)
return 0;
}
- if (GET_CODE (accumulator) == SUBREG)
+ if (SUBREG_P (accumulator))
accumulator = SUBREG_REG (accumulator);
if (!REG_P (accumulator))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c67b7c97dcc..2a5359c26ec 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -5347,7 +5347,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
to facilitate possible combining with a cmp into 'ands'. */
if (mode == SImode
&& GET_CODE (*op0) == ZERO_EXTEND
- && GET_CODE (XEXP (*op0, 0)) == SUBREG
+ && SUBREG_P (XEXP (*op0, 0))
&& GET_MODE (XEXP (*op0, 0)) == QImode
&& GET_MODE (SUBREG_REG (XEXP (*op0, 0))) == SImode
&& subreg_lowpart_p (XEXP (*op0, 0))
@@ -8973,7 +8973,7 @@ arm_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
#define REG_OR_SUBREG_REG(X) \
(REG_P (X) \
- || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))))
+ || (SUBREG_P (X) && REG_P (SUBREG_REG (X))))
#define REG_OR_SUBREG_RTX(X) \
(REG_P (X) ? (X) : SUBREG_REG (X))
@@ -10514,7 +10514,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
if (XEXP (x, 1) == const0_rtx
&& !(REG_P (XEXP (x, 0))
- || (GET_CODE (XEXP (x, 0)) == SUBREG
+ || (SUBREG_P (XEXP (x, 0))
&& REG_P (SUBREG_REG (XEXP (x, 0))))))
{
*cost = rtx_cost (XEXP (x, 0), op0mode, COMPARE, 0, speed_p);
@@ -13395,7 +13395,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
rtx offset;
/* Convert a subreg of a mem into the mem itself. */
- if (GET_CODE (operands[nops + i]) == SUBREG)
+ if (SUBREG_P (operands[nops + i]))
operands[nops + i] = alter_subreg (operands + (nops + i), true);
gcc_assert (MEM_P (operands[nops + i]));
@@ -13408,11 +13408,11 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
offset = const0_rtx;
if ((REG_P (reg = XEXP (operands[nops + i], 0))
- || (GET_CODE (reg) == SUBREG
+ || (SUBREG_P (reg)
&& REG_P (reg = SUBREG_REG (reg))))
|| (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
&& ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
- || (GET_CODE (reg) == SUBREG
+ || (SUBREG_P (reg)
&& REG_P (reg = SUBREG_REG (reg))))
&& (CONST_INT_P (offset
= XEXP (XEXP (operands[nops + i], 0), 1)))))
@@ -13549,7 +13549,7 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,
rtx offset;
/* Convert a subreg of a mem into the mem itself. */
- if (GET_CODE (operands[nops + i]) == SUBREG)
+ if (SUBREG_P (operands[nops + i]))
operands[nops + i] = alter_subreg (operands + (nops + i), true);
gcc_assert (MEM_P (operands[nops + i]));
@@ -13562,11 +13562,11 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,
offset = const0_rtx;
if ((REG_P (reg = XEXP (operands[nops + i], 0))
- || (GET_CODE (reg) == SUBREG
+ || (SUBREG_P (reg)
&& REG_P (reg = SUBREG_REG (reg))))
|| (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
&& ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
- || (GET_CODE (reg) == SUBREG
+ || (SUBREG_P (reg)
&& REG_P (reg = SUBREG_REG (reg))))
&& (CONST_INT_P (offset
= XEXP (XEXP (operands[nops + i], 0), 1)))))
@@ -14877,7 +14877,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
/* A compare with a shifted operand. Because of canonicalization, the
comparison will have to be swapped when we emit the assembler. */
if (GET_MODE (y) == SImode
- && (REG_P (y) || (GET_CODE (y) == SUBREG))
+ && (REG_P (y) || (SUBREG_P (y)))
&& (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
|| GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
|| GET_CODE (x) == ROTATERT))
@@ -14886,7 +14886,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
/* This operation is performed swapped, but since we only rely on the Z
flag we don't need an additional mode. */
if (GET_MODE (y) == SImode
- && (REG_P (y) || (GET_CODE (y) == SUBREG))
+ && (REG_P (y) || (SUBREG_P (y)))
&& GET_CODE (x) == NEG
&& (op == EQ || op == NE))
return CC_Zmode;
@@ -14898,7 +14898,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
if (GET_MODE (x) == SImode
&& GET_CODE (x) == ASHIFT
&& CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 24
- && GET_CODE (XEXP (x, 0)) == SUBREG
+ && SUBREG_P (XEXP (x, 0))
&& MEM_P (SUBREG_REG (XEXP (x, 0)))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
&& (op == EQ || op == NE
@@ -15087,7 +15087,7 @@ arm_reload_in_hi (rtx *operands)
rtx base, scratch;
HOST_WIDE_INT offset = 0;
- if (GET_CODE (ref) == SUBREG)
+ if (SUBREG_P (ref))
{
offset = SUBREG_BYTE (ref);
ref = SUBREG_REG (ref);
@@ -15215,7 +15215,7 @@ arm_reload_out_hi (rtx *operands)
rtx base, scratch;
HOST_WIDE_INT offset = 0;
- if (GET_CODE (ref) == SUBREG)
+ if (SUBREG_P (ref))
{
offset = SUBREG_BYTE (ref);
ref = SUBREG_REG (ref);
@@ -15546,7 +15546,7 @@ mem_ok_for_ldrd_strd (rtx mem, rtx *base, rtx *offset, HOST_WIDE_INT *align)
return false;
/* Can't deal with subregs. */
- if (GET_CODE (mem) == SUBREG)
+ if (SUBREG_P (mem))
return false;
gcc_assert (MEM_P (mem));
@@ -15615,7 +15615,7 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
return false;
offsets[i] = INTVAL (cur_offset);
- if (GET_CODE (operands[i]) == SUBREG)
+ if (SUBREG_P (operands[i]))
{
tmp = SUBREG_REG (operands[i]);
gcc_assert (GET_MODE (operands[i]) == GET_MODE (tmp));
@@ -15841,7 +15841,7 @@ valid_operands_ldrd_strd (rtx *operands, bool load)
return false;
offsets[i] = INTVAL (cur_offset);
- if (GET_CODE (operands[i]) == SUBREG)
+ if (SUBREG_P (operands[i]))
return false;
}
@@ -29679,13 +29679,13 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in,
gcc_assert (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT);
gcc_assert (out
- && (REG_P (out) || GET_CODE (out) == SUBREG)
+ && (REG_P (out) || SUBREG_P (out))
&& GET_MODE (out) == DImode);
gcc_assert (in
- && (REG_P (in) || GET_CODE (in) == SUBREG)
+ && (REG_P (in) || SUBREG_P (in))
&& GET_MODE (in) == DImode);
gcc_assert (amount
- && (((REG_P (amount) || GET_CODE (amount) == SUBREG)
+ && (((REG_P (amount) || SUBREG_P (amount))
&& GET_MODE (amount) == SImode)
|| CONST_INT_P (amount)));
gcc_assert (scratch1 == NULL
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 4866e1e4b7d..b2a2bc8cf39 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1240,7 +1240,7 @@ enum reg_class
? GENERAL_REGS : \
(((MODE) == HImode && ! arm_arch4 \
&& (MEM_P (X) \
- || ((REG_P (X) || GET_CODE (X) == SUBREG) \
+ || ((REG_P (X) || SUBREG_P (X)) \
&& true_regnum (X) == -1))) \
? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index ccc48a57dda..5eadcc58df6 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2809,7 +2809,7 @@
target = copy_rtx (operands[0]);
/* Avoid using a subreg as a subtarget, and avoid writing a paradoxical
subreg as the final target. */
- if (GET_CODE (target) == SUBREG)
+ if (SUBREG_P (target))
{
subtarget = gen_reg_rtx (SImode);
if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (target)))
@@ -2919,7 +2919,7 @@
{
/* If TARGET is still a SUBREG, then it must be wider than a word,
so we must be careful only to set the subword we were asked to. */
- if (GET_CODE (target) == SUBREG)
+ if (SUBREG_P (target))
emit_move_insn (target, subtarget);
else
emit_move_insn (target, gen_lowpart (GET_MODE (target), subtarget));
@@ -4357,7 +4357,7 @@
rtx tmp = gen_reg_rtx (SImode);
/* We may get a paradoxical subreg here. Strip it off. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& GET_MODE (dest) == SImode
&& GET_MODE (SUBREG_REG (dest)) == HImode)
dest = SUBREG_REG (dest);
@@ -4441,7 +4441,7 @@
rtx tmp = gen_reg_rtx (SImode);
/* We may get a paradoxical subreg here. Strip it off. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& GET_MODE (dest) == SImode
&& GET_MODE (SUBREG_REG (dest)) == HImode)
dest = SUBREG_REG (dest);
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 25f86471ded..de040cec465 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -21,7 +21,7 @@
(define_predicate "s_register_operand"
(match_code "reg,subreg")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
/* We don't consider registers whose class is NO_REGS
to be a register operand. */
@@ -91,7 +91,7 @@
(define_predicate "arm_general_register_operand"
(match_code "reg,subreg")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return (REG_P (op)
@@ -107,7 +107,7 @@
(define_predicate "vfp_register_operand"
(match_code "reg,subreg")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
/* We don't consider registers whose class is NO_REGS
@@ -466,7 +466,7 @@
if (s_register_operand (op, mode))
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
@@ -483,7 +483,7 @@
if (s_register_operand (op, mode))
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 7f8424b5f5d..716e7345d50 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -2875,7 +2875,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
}
*total = cost2;
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += set_src_cost (op0, mode, speed);
#if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
towards creating too many induction variables. */
@@ -2890,7 +2890,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
|| !satisfies_constraint_Ks7 (op1))
*total += rtx_cost (op1, mode, PLUS, 1, speed);
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, PLUS, 0, speed);
}
return true;
@@ -2913,7 +2913,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, code, 0, speed);
return true;
@@ -2938,7 +2938,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
}
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, code, 0, speed);
if (mode == DImode)
@@ -2997,10 +2997,10 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
*total = COSTS_N_INSNS (3);
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, MULT, 0, speed);
if (!REG_P (op1)
- && (GET_CODE (op1) != SUBREG || !REG_P (SUBREG_REG (op1))))
+ && (!SUBREG_P (op1) || !REG_P (SUBREG_REG (op1))))
*total += rtx_cost (op1, mode, MULT, 1, speed);
}
return true;
diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md
index 04eb584df0f..fa29cea79c3 100644
--- a/gcc/config/bfin/predicates.md
+++ b/gcc/config/bfin/predicates.md
@@ -76,7 +76,7 @@
(define_predicate "valid_reg_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REGNO (op) < FIRST_PSEUDO_REGISTER)
return targetm.hard_regno_mode_ok (REGNO (op), mode);
@@ -122,7 +122,7 @@
(match_operand 0 "register_operand")
{
unsigned int regno;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -180,7 +180,7 @@
(define_predicate "register_no_elim_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return !(op == arg_pointer_rtx
|| op == frame_pointer_rtx
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index fe78ed0dfce..dab63cb3011 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -6175,10 +6175,10 @@ c6x_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, int *total,
*total = COSTS_N_INSNS (speed ? 2 : 1);
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, MULT, 0, speed);
if (op1 && !REG_P (op1)
- && (GET_CODE (op1) != SUBREG || !REG_P (SUBREG_REG (op1))))
+ && (!SUBREG_P (op1) || !REG_P (SUBREG_REG (op1))))
*total += rtx_cost (op1, mode, MULT, 1, speed);
return true;
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index 2b35d6717cb..1404363f8f8 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -632,7 +632,7 @@
(match_operand:SISFVM 1 "general_operand"
"a,b,?b,?a,Is5,IsB,S0,S0,Si,Q, R, R, Q, a,?a, b,?b"))]
"(GET_CODE (operands[0]) != MEM || REG_P (operands[1])
- || (GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))))"
+ || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))"
"@
%|%.\\tmv\\t%$\\t%1, %0
%|%.\\tmv\\t%$\\t%1, %0
@@ -666,7 +666,7 @@
(match_operand:DIDFVM 1 "general_operand"
"a,b,?b,?a,iF,Q, R, R, Q, a,?a, b,?b"))]
"(!MEM_P (operands[0]) || REG_P (operands[1])
- || (GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))))"
+ || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))"
{
if (MEM_P (operands[1]) && TARGET_LDDW)
return "%|%.\\tlddw\\t%$\\t%1, %0";
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 4cdb58b06bb..0dc9435078d 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -715,7 +715,7 @@ cr16_addr_reg_p (rtx addr_reg)
if (REG_P (addr_reg))
reg = addr_reg;
- else if ((GET_CODE (addr_reg) == SUBREG)
+ else if ((SUBREG_P (addr_reg))
&& REG_P (SUBREG_REG (addr_reg))
&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (addr_reg)))
<= UNITS_PER_WORD))
diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c
index 67d7c316841..2073f35f119 100644
--- a/gcc/config/cris/cris.c
+++ b/gcc/config/cris/cris.c
@@ -2890,7 +2890,7 @@ cris_split_movdx (rtx *operands)
/* We used to have to handle (SUBREG (MEM)) here, but that should no
longer happen; after reload there are no SUBREGs any more, and we're
only called after reload. */
- CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
+ CRIS_ASSERT (!SUBREG_P (dest) && !SUBREG_P (src));
start_sequence ();
if (REG_P (dest))
diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h
index 2c77ab865b4..8006c25390b 100644
--- a/gcc/config/cris/cris.h
+++ b/gcc/config/cris/cris.h
@@ -44,7 +44,7 @@ along with GCC; see the file COPYING3. If not see
/* Replacement for REG_P since it does not match SUBREGs. Happens for
testcase Axis-20000320 with gcc-2.9x. */
#define REG_S_P(x) \
- (REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (XEXP (x, 0))))
+ (REG_P (x) || (SUBREG_P (x) && REG_P (XEXP (x, 0))))
/* Last register in main register bank r0..r15. */
#define CRIS_LAST_GENERAL_REGISTER 15
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 6d2192a5096..fd2291f176c 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -2313,7 +2313,7 @@ csky_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
regno = true_regnum (x);
else
{
- while (GET_CODE (x) == SUBREG)
+ while (SUBREG_P (x))
{
off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
GET_MODE (SUBREG_REG (x)),
@@ -2325,7 +2325,7 @@ csky_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
regno = REGNO (x) + off;
}
}
- else if (REG_P (x) || GET_CODE (x) == SUBREG)
+ else if (REG_P (x) || SUBREG_P (x))
regno = true_regnum (x);
/* We always require a general register when copying anything to
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 9089c4673dc..8dea5b9f33c 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -981,7 +981,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
#endif /* HAVE_lo_sum */
{
if (REG_P (orig)
- || GET_CODE (orig) == SUBREG)
+ || SUBREG_P (orig))
{
return orig;
}
diff --git a/gcc/config/epiphany/epiphany.md b/gcc/config/epiphany/epiphany.md
index be9ea9ab5aa..354a21f5c41 100644
--- a/gcc/config/epiphany/epiphany.md
+++ b/gcc/config/epiphany/epiphany.md
@@ -335,10 +335,10 @@
&& !reload_in_progress
&& (GET_CODE (operands[0]) == MEM || GET_CODE (operands[1]) == MEM)
&& !misaligned_operand (operands[1], <MODE>mode)
- && (GET_CODE (operands[0]) != SUBREG
+ && (!SUBREG_P (operands[0])
|| (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
!= GET_MODE_SIZE (<MODE>mode)
- && GET_CODE (operands[1]) != SUBREG)))
+ && !SUBREG_P (operands[1]))))
{
operands[0]
= simplify_gen_subreg (DImode, operands[0], <MODE>mode, 0);
@@ -2579,8 +2579,8 @@
gcc_assert (!reg_overlap_mentioned_p (last_out, xop[i])
/* ??? reg_overlap_mentioned_p doesn't understand
about multi-word SUBREGs. */
- || (GET_CODE (last_out) == SUBREG
- && GET_CODE (xop[i]) == SUBREG
+ || (SUBREG_P (last_out)
+ && SUBREG_P (xop[i])
&& SUBREG_REG (last_out) == SUBREG_REG (xop[i])
&& ((SUBREG_BYTE (last_out) & -UNITS_PER_WORD)
!= (SUBREG_BYTE (xop[i]) & -UNITS_PER_WORD))));
diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md
index 6804a75a290..1d881a22d50 100644
--- a/gcc/config/epiphany/predicates.md
+++ b/gcc/config/epiphany/predicates.md
@@ -62,7 +62,7 @@
if (!register_operand (op, mode))
return 0;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = XEXP (op, 0);
regno = REGNO (op);
return regno >= FIRST_PSEUDO_REGISTER || regno <= 63;
@@ -84,7 +84,7 @@
if (!register_operand (op, mode))
return 0;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = XEXP (op, 0);
regno = REGNO (op);
return (regno >= FIRST_PSEUDO_REGISTER || regno <= 63
@@ -96,7 +96,7 @@
(define_predicate "add_operand"
(match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return add_reg_operand (op, mode);
return satisfies_constraint_L (op) || satisfies_constraint_CnL (op);
})
@@ -105,7 +105,7 @@
(define_predicate "arith_operand"
(match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
return satisfies_constraint_L (op);
})
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index b8670bbdb14..f19dbdabd81 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -291,7 +291,7 @@
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
"INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128
- && (GET_CODE (operands[0]) != SUBREG
+ && (!SUBREG_P (operands[0])
|| SCALAR_INT_MODE_P (GET_MODE (XEXP (operands[0], 0))))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0) (sign_extend:SI (match_dup 2)))]
@@ -654,7 +654,7 @@
""
"{
if ( REG_P (operands[2])
- || GET_CODE (operands[2]) == SUBREG)
+ || SUBREG_P (operands[2]))
emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
else if (!CONST_INT_P (operands[2]))
emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md
index f8b9b781e28..330a74523a5 100644
--- a/gcc/config/fr30/predicates.md
+++ b/gcc/config/fr30/predicates.md
@@ -72,7 +72,7 @@
if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
switch (GET_CODE (op))
@@ -100,7 +100,7 @@
if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == MEM)
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 72f867d3306..a1df8153a22 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -2564,7 +2564,7 @@ frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
fputs ("@(", stream);
if (!x0)
fputs (reg_names[GPR_R0], stream);
- else if (REG_P (x0) || GET_CODE (x0) == SUBREG)
+ else if (REG_P (x0) || SUBREG_P (x0))
frv_print_operand_memory_reference_reg (stream, x0);
else
fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
@@ -3368,7 +3368,7 @@ frv_legitimate_address_p_1 (machine_mode mode,
x0 = XEXP (x, 0);
x1 = XEXP (x, 1);
- if (GET_CODE (x0) == SUBREG)
+ if (SUBREG_P (x0))
x0 = SUBREG_REG (x0);
if (!REG_P (x0))
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index c3724de35e6..bbe55939a62 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -25,7 +25,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -51,7 +51,7 @@
if (reload_in_progress)
{
rtx tmp = op;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
@@ -86,7 +86,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -118,7 +118,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -146,7 +146,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -175,7 +175,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -200,7 +200,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -747,7 +747,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -771,7 +771,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -805,7 +805,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -840,7 +840,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -871,7 +871,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -903,7 +903,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -934,7 +934,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -965,7 +965,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -1447,7 +1447,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 0006583b11e..bc57f0d7c33 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -611,7 +611,7 @@ gcn_can_split_p (machine_mode, rtx op)
{
if (vgpr_vector_mode_p (GET_MODE (op)))
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op))
return true;
@@ -1015,7 +1015,7 @@ gcn_gen_undef (machine_mode mode)
static bool
gcn_address_register_p (rtx reg, machine_mode mode, bool strict)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg))
@@ -1047,7 +1047,7 @@ gcn_address_register_p (rtx reg, machine_mode mode, bool strict)
static bool
gcn_vec_address_register_p (rtx reg, machine_mode mode, bool strict)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg))
@@ -1917,7 +1917,7 @@ gcn_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
{
reg_class_t result = NO_REGS;
bool spilled_pseudo =
- (REG_P (x) || GET_CODE (x) == SUBREG) && true_regnum (x) == -1;
+ (REG_P (x) || SUBREG_P (x)) && true_regnum (x) == -1;
if (dump_file && (dump_flags & TDF_DETAILS))
{
@@ -1925,7 +1925,7 @@ gcn_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
dump_value_slim (dump_file, x, 1);
fprintf (dump_file, " %s %s:%s", (in_p ? "->" : "<-"),
reg_class_names[rclass], GET_MODE_NAME (reload_mode));
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
fprintf (dump_file, " (true regnum: %d \"%s\")", true_regnum (x),
(true_regnum (x) >= 0
&& true_regnum (x) < FIRST_PSEUDO_REGISTER
diff --git a/gcc/config/gcn/predicates.md b/gcc/config/gcn/predicates.md
index 5b54f49f3cd..5e08a8bf32b 100644
--- a/gcc/config/gcn/predicates.md
+++ b/gcc/config/gcn/predicates.md
@@ -21,7 +21,7 @@
(define_predicate "gcn_conditional_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op) || GET_MODE (op) != BImode)
@@ -37,7 +37,7 @@
(define_predicate "gcn_ssrc_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op))
@@ -49,7 +49,7 @@
(define_predicate "gcn_sdst_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op))
@@ -61,7 +61,7 @@
(define_predicate "gcn_vgpr_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op))
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 44a4352f36a..5e1fe1b682b 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -5840,7 +5840,7 @@ static int
h8300_rtx_ok_for_base_p (rtx x, int strict)
{
/* Strip off SUBREG if any. */
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 1b495be4582..082ef9a7f74 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -3027,7 +3027,7 @@
/* Optimize the case where we're extracting into a paradoxical
subreg. It's only necessary to extend to the inner reg. */
- if (GET_CODE (operands[0]) == SUBREG
+ if (SUBREG_P (operands[0])
&& subreg_lowpart_p (operands[0])
&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
< GET_MODE_SIZE (GET_MODE (operands[0])))
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index 5f30de3c80a..4eeb34bb75d 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -347,7 +347,7 @@
if (REG_P (op))
return 1;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
return 1;
return (GET_CODE (op) == MEM
&& satisfies_constraint_U (op));
@@ -386,7 +386,7 @@
(define_predicate "register_no_sp_elim_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return !(op == stack_pointer_rtx
|| op == arg_pointer_rtx
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index a266f2a6fa8..a5813a80bfa 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -1004,7 +1004,7 @@ static bool
ia64_legitimate_address_reg (const_rtx reg, bool strict)
{
if ((REG_P (reg) && ia64_reg_ok_for_base_p (reg, strict))
- || (GET_CODE (reg) == SUBREG && REG_P (XEXP (reg, 0))
+ || (SUBREG_P (reg) && REG_P (XEXP (reg, 0))
&& ia64_reg_ok_for_base_p (XEXP (reg, 0), strict)))
return true;
@@ -1647,7 +1647,7 @@ ia64_split_tmode_move (rtx operands[])
static rtx
spill_xfmode_rfmode_operand (rtx in, int force, machine_mode mode)
{
- if (GET_CODE (in) == SUBREG
+ if (SUBREG_P (in)
&& GET_MODE (SUBREG_REG (in)) == TImode
&& REG_P (SUBREG_REG (in)))
{
@@ -1674,7 +1674,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
{
rtx op0 = operands[0];
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = SUBREG_REG (op0);
/* We must support XFmode loads into general registers for stdarg/vararg,
@@ -1693,14 +1693,14 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
gcc_assert (can_create_pseudo_p ());
/* Struct to register can just use TImode instead. */
- if ((GET_CODE (operands[1]) == SUBREG
+ if ((SUBREG_P (operands[1])
&& GET_MODE (SUBREG_REG (operands[1])) == TImode)
|| (REG_P (operands[1])
&& GR_REGNO_P (REGNO (operands[1]))))
{
rtx op1 = operands[1];
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = SUBREG_REG (op1);
else
op1 = gen_rtx_REG (TImode, REGNO (op1));
@@ -5898,7 +5898,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
{
int regno = -1;
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
regno = true_regnum (x);
switch (rclass)
@@ -9626,7 +9626,7 @@ ia64_st_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
gcc_assert (dest);
reg = SET_DEST (dest);
gcc_assert (reg);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -9650,7 +9650,7 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
gcc_assert (dest);
reg = SET_DEST (dest);
gcc_assert (reg);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -9668,7 +9668,7 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
mem = XEXP (mem, 1);
}
- while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
+ while (SUBREG_P (mem) || GET_CODE (mem) == ZERO_EXTEND)
mem = XEXP (mem, 0);
if (GET_CODE (mem) == UNSPEC)
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index 4a539cdf423..c1f3e09322c 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -380,7 +380,7 @@
(match_operand 0 "register_operand")
{
unsigned int regno;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -392,7 +392,7 @@
(match_operand 0 "register_operand")
{
unsigned int regno;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -404,7 +404,7 @@
(match_operand 0 "register_operand")
{
unsigned int regno;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -421,7 +421,7 @@
if (GET_CODE (op) == MEM)
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -436,7 +436,7 @@
if (GET_CODE (op) == MEM)
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -451,7 +451,7 @@
if (GET_CODE (op) == MEM)
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index b5e2754dc3e..2092093b877 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -331,7 +331,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
&& ! (CONST_INT_P (xinsn) && ! SMALL_INT (xinsn)))
return 1;
- while (GET_CODE (xinsn) == SUBREG)
+ while (SUBREG_P (xinsn))
xinsn = SUBREG_REG (xinsn);
if (REG_P (xinsn)
@@ -343,7 +343,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
rtx xlow0 = XEXP (xinsn, 0);
rtx xlow1 = XEXP (xinsn, 1);
- while (GET_CODE (xlow0) == SUBREG)
+ while (SUBREG_P (xlow0))
xlow0 = SUBREG_REG (xlow0);
if (REG_P (xlow0)
&& iq2000_reg_mode_ok_for_base_p (xlow0, mode, strict)
@@ -358,11 +358,11 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
enum rtx_code code0;
enum rtx_code code1;
- while (GET_CODE (xplus0) == SUBREG)
+ while (SUBREG_P (xplus0))
xplus0 = SUBREG_REG (xplus0);
code0 = GET_CODE (xplus0);
- while (GET_CODE (xplus1) == SUBREG)
+ while (SUBREG_P (xplus1))
xplus1 = SUBREG_REG (xplus1);
code1 = GET_CODE (xplus1);
@@ -434,7 +434,7 @@ iq2000_fill_delay_slot (const char *ret, enum delay_type type, rtx operands[],
if (set_reg == 0)
return ret;
- while (GET_CODE (set_reg) == SUBREG)
+ while (SUBREG_P (set_reg))
set_reg = SUBREG_REG (set_reg);
mode = GET_MODE (set_reg);
@@ -956,7 +956,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
branch_p = (result == 0);
if (branch_p)
{
- if (REG_P (cmp0) || GET_CODE (cmp0) == SUBREG)
+ if (REG_P (cmp0) || SUBREG_P (cmp0))
{
/* Comparisons against zero are simple branches. */
if (CONST_INT_P (cmp1) && INTVAL (cmp1) == 0)
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index 095a9a6818f..e52354eb8d8 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -138,7 +138,7 @@
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) == MEM
- || (GET_CODE (operands[0]) == SUBREG
+ || (SUBREG_P (operands[0])
&& GET_CODE (SUBREG_REG (operands[0])) == MEM))
{
/* Source operand for store must be in a register. */
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 1ff54b41363..922ea03ce80 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -1770,7 +1770,7 @@ m32c_legitimate_address_p (machine_mode mode, rtx x, bool strict)
/* case SB_REGNO: */
return 1;
default:
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
return 0;
if (IS_PSEUDO (reg, strict))
return 1;
@@ -3138,7 +3138,7 @@ m32c_illegal_subreg_p (rtx op)
return true;
}
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
return false;
dest_mode = GET_MODE (op);
@@ -3199,9 +3199,9 @@ m32c_mov_ok (rtx * operands, machine_mode mode ATTRIBUTE_UNUSED)
debug_rtx (op1);
#endif
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = XEXP (op0, 0);
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = XEXP (op1, 0);
if (GET_CODE (op0) == MEM
@@ -3244,7 +3244,7 @@ m32c_subreg (machine_mode outer,
/* Converting MEMs to different types that are the same size, we
just rewrite them. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_BYTE (x) == 0
&& GET_CODE (SUBREG_REG (x)) == MEM
&& (GET_MODE_SIZE (GET_MODE (x))
@@ -3260,7 +3260,7 @@ m32c_subreg (machine_mode outer,
&& (GET_CODE (XEXP (x, 0)) == PRE_DEC
|| GET_CODE (XEXP (x, 0)) == POST_INC))
return gen_rtx_MEM (outer, XEXP (x, 0));
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& GET_CODE (XEXP (x, 0)) == MEM
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
|| GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
@@ -3269,7 +3269,7 @@ m32c_subreg (machine_mode outer,
if (!REG_P (x))
{
rtx r = simplify_gen_subreg (outer, x, inner, byte);
- if (GET_CODE (r) == SUBREG
+ if (SUBREG_P (r)
&& GET_CODE (x) == MEM
&& MEM_VOLATILE_P (x))
{
@@ -3906,7 +3906,7 @@ m32c_expand_insv (rtx *operands)
mask = 1 << INTVAL (operands[2]);
op0 = operands[0];
- if (GET_CODE (op0) == SUBREG
+ if (SUBREG_P (op0)
&& SUBREG_BYTE (op0) == 0)
{
rtx sub = SUBREG_REG (op0);
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index 13e5675040e..044718fdc69 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -1064,9 +1064,9 @@ gen_split_move_double (rtx operands[])
/* We might have (SUBREG (MEM)) here, so just get rid of the
subregs to make this code simpler. It is safe to call
alter_subreg any time after reload. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
alter_subreg (&dest, true);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
alter_subreg (&src, true);
start_sequence ();
@@ -2462,13 +2462,13 @@ m32r_not_same_reg (rtx a, rtx b)
int reg_a = -1;
int reg_b = -2;
- while (GET_CODE (a) == SUBREG)
+ while (SUBREG_P (a))
a = SUBREG_REG (a);
if (REG_P (a))
reg_a = REGNO (a);
- while (GET_CODE (b) == SUBREG)
+ while (SUBREG_P (b))
b = SUBREG_REG (b);
if (REG_P (b))
diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index e944363fd9b..3e191012659 100644
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -366,7 +366,7 @@
"register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
"*
{
- if (REG_P (operands[0]) || GET_CODE (operands[1]) == SUBREG)
+ if (REG_P (operands[0]) || SUBREG_P (operands[1]))
{
switch (GET_CODE (operands[1]))
{
@@ -407,7 +407,7 @@
}
else if (MEM_P (operands[0])
- && (REG_P (operands[1]) || GET_CODE (operands[1]) == SUBREG))
+ && (REG_P (operands[1]) || SUBREG_P (operands[1])))
{
if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
diff --git a/gcc/config/m32r/predicates.md b/gcc/config/m32r/predicates.md
index a469c976bc3..1d7e195f5bd 100644
--- a/gcc/config/m32r/predicates.md
+++ b/gcc/config/m32r/predicates.md
@@ -22,7 +22,7 @@
(define_predicate "reg_or_zero_operand"
(match_code "reg,subreg,const_int")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
@@ -277,7 +277,7 @@
(define_predicate "reg_or_int16_operand"
(match_code "reg,subreg,const_int")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
return 0;
@@ -289,7 +289,7 @@
(define_predicate "reg_or_uint16_operand"
(match_code "reg,subreg,const_int")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
return 0;
@@ -302,7 +302,7 @@
(define_predicate "reg_or_cmp_int16_operand"
(match_code "reg,subreg,const_int")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
return 0;
@@ -319,7 +319,7 @@
{
HOST_WIDE_INT value;
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 5c02c6eb3df..0fb4b059daa 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -1863,7 +1863,7 @@ bool
m68k_legitimate_base_reg_p (rtx x, bool strict_p)
{
/* Allow SUBREG everywhere we allow REG. This results in better code. */
- if (!strict_p && GET_CODE (x) == SUBREG)
+ if (!strict_p && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -1878,7 +1878,7 @@ m68k_legitimate_base_reg_p (rtx x, bool strict_p)
bool
m68k_legitimate_index_reg_p (rtx x, bool strict_p)
{
- if (!strict_p && GET_CODE (x) == SUBREG)
+ if (!strict_p && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -3685,7 +3685,7 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
operand0 = reg_equiv_mem (REGNO (operand0));
else if (scratch_reg
- && reload_in_progress && GET_CODE (operand0) == SUBREG
+ && reload_in_progress && SUBREG_P (operand0)
&& REG_P (SUBREG_REG (operand0))
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
{
@@ -3702,7 +3702,7 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
operand1 = reg_equiv_mem (REGNO (operand1));
else if (scratch_reg
- && reload_in_progress && GET_CODE (operand1) == SUBREG
+ && reload_in_progress && SUBREG_P (operand1)
&& REG_P (SUBREG_REG (operand1))
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
{
@@ -3728,12 +3728,12 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
if (fp_reg_operand (operand0, mode)
&& ((GET_CODE (operand1) == MEM
&& ! memory_address_p (DFmode, XEXP (operand1, 0)))
- || ((GET_CODE (operand1) == SUBREG
+ || ((SUBREG_P (operand1)
&& GET_CODE (XEXP (operand1, 0)) == MEM
&& !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
&& scratch_reg)
{
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
operand1 = XEXP (operand1, 0);
/* SCRATCH_REG will hold an address. We want
@@ -3759,12 +3759,12 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
else if (fp_reg_operand (operand1, mode)
&& ((GET_CODE (operand0) == MEM
&& ! memory_address_p (DFmode, XEXP (operand0, 0)))
- || ((GET_CODE (operand0) == SUBREG)
+ || ((SUBREG_P (operand0))
&& GET_CODE (XEXP (operand0, 0)) == MEM
&& !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
&& scratch_reg)
{
- if (GET_CODE (operand0) == SUBREG)
+ if (SUBREG_P (operand0))
operand0 = XEXP (operand0, 0);
/* SCRATCH_REG will hold an address and maybe the actual data. We want
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index d4f417a16e9..4df4551fd95 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -929,7 +929,7 @@ mcore_is_dead (rtx_insn *first, rtx reg)
rtx_insn *insn;
/* For mcore, subregs can't live independently of their parent regs. */
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
/* Dies immediately. */
@@ -2292,14 +2292,14 @@ is_cond_candidate (rtx insn)
dst = XEXP (pat, 0);
if ((!REG_P (dst) &&
- GET_CODE (dst) != SUBREG) ||
+ !SUBREG_P (dst)) ||
GET_MODE (dst) != SImode)
return COND_NO;
src = XEXP (pat, 1);
if ((REG_P (src) ||
- (GET_CODE (src) == SUBREG &&
+ (SUBREG_P (src) &&
REG_P (SUBREG_REG (src)))) &&
GET_MODE (src) == SImode)
return COND_MOV_INSN;
@@ -2308,7 +2308,7 @@ is_cond_candidate (rtx insn)
return COND_CLR_INSN;
else if (GET_CODE (src) == PLUS &&
(REG_P (XEXP (src, 0)) ||
- (GET_CODE (XEXP (src, 0)) == SUBREG &&
+ (SUBREG_P (XEXP (src, 0)) &&
REG_P (SUBREG_REG (XEXP (src, 0))))) &&
GET_MODE (XEXP (src, 0)) == SImode &&
CONST_INT_P (XEXP (src, 1)) &&
@@ -2321,7 +2321,7 @@ is_cond_candidate (rtx insn)
CONST_INT_P (XEXP (src, 1)) &&
INTVAL (XEXP (src, 1)) == -1)) &&
(REG_P (XEXP (src, 0)) ||
- (GET_CODE (XEXP (src, 0)) == SUBREG &&
+ (SUBREG_P (XEXP (src, 0)) &&
REG_P (SUBREG_REG (XEXP (src, 0))))) &&
GET_MODE (XEXP (src, 0)) == SImode)
return COND_DEC_INSN;
@@ -2684,10 +2684,10 @@ int
mcore_is_same_reg (rtx x, rtx y)
{
/* Strip any and all of the subreg wrappers. */
- while (GET_CODE (x) == SUBREG)
+ while (SUBREG_P (x))
x = SUBREG_REG (x);
- while (GET_CODE (y) == SUBREG)
+ while (SUBREG_P (y))
y = SUBREG_REG (y);
if (REG_P (x) && REG_P (y) && REGNO(x) == REGNO(y))
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index 755a322139c..c71cb67fdb6 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -96,7 +96,7 @@
(ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
(const_int 7))
(const_int 0)))]
- "GET_CODE(operands[0]) == SUBREG &&
+ "SUBREG_P (operands[0]) &&
GET_MODE(SUBREG_REG(operands[0])) == QImode"
"btsti %0,7"
[(set_attr "type" "shift")])
@@ -106,7 +106,7 @@
(ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
(const_int 15))
(const_int 0)))]
- "GET_CODE(operands[0]) == SUBREG &&
+ "SUBREG_P (operands[0]) &&
GET_MODE(SUBREG_REG(operands[0])) == HImode"
"btsti %0,15"
[(set_attr "type" "shift")])
@@ -1937,7 +1937,7 @@
(const_int 0))
(match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
(match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
- "GET_CODE (operands[1]) == SUBREG &&
+ "SUBREG_P (operands[1]) &&
GET_MODE (SUBREG_REG (operands[1])) == QImode"
"@
btsti %1,7\;movf %0,%2
@@ -2024,7 +2024,7 @@
(const_int 0))
(match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
(match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
- "GET_CODE (operands[1]) == SUBREG &&
+ "SUBREG_P (operands[1]) &&
GET_MODE (SUBREG_REG (operands[1])) == QImode"
"@
btsti %1,7\;movt %0,%2
@@ -2704,7 +2704,7 @@
(set (match_operand:SI 2 "mcore_arith_reg_operand" "")
(and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
(match_dup 0)))]
- "GET_CODE (operands[3]) == SUBREG &&
+ "SUBREG_P (operands[3]) &&
GET_MODE (SUBREG_REG (operands[3])) == QImode &&
mcore_num_zeros (INTVAL (operands[1]) | 0xffffff00) == 1 &&
mcore_is_dead (insn, operands[0])"
@@ -2721,7 +2721,7 @@
(set (match_operand:SI 2 "mcore_arith_reg_operand" "")
(and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
(match_dup 0)))]
- "GET_CODE (operands[3]) == SUBREG &&
+ "SUBREG_P (operands[3]) &&
GET_MODE (SUBREG_REG (operands[3])) == HImode &&
mcore_num_zeros (INTVAL (operands[1]) | 0xffff0000) == 1 &&
operands[2] == operands[3] &&
diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md
index c29792cc520..5bc901e55ea 100644
--- a/gcc/config/mcore/predicates.md
+++ b/gcc/config/mcore/predicates.md
@@ -25,7 +25,7 @@
if (! register_operand (op, mode))
return 0;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REG_P (op))
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index f9c2adf9ab7..800baefc070 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -406,7 +406,7 @@ microblaze_valid_base_register_p (rtx x,
machine_mode mode ATTRIBUTE_UNUSED,
int strict)
{
- if (!strict && GET_CODE (x) == SUBREG)
+ if (!strict && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -671,7 +671,7 @@ microblaze_valid_index_register_p (rtx x,
machine_mode mode ATTRIBUTE_UNUSED,
int strict)
{
- if (!strict && GET_CODE (x) == SUBREG)
+ if (!strict && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -3473,7 +3473,7 @@ microblaze_expand_shift (rtx operands[])
{
gcc_assert ((CONST_INT_P (operands[2]))
|| (REG_P (operands[2]))
- || (GET_CODE (operands[2]) == SUBREG));
+ || (SUBREG_P (operands[2])));
/* Shift by one -- generate pattern. */
if ((CONST_INT_P (operands[2])) && (INTVAL (operands[2]) == 1))
@@ -3484,9 +3484,9 @@ microblaze_expand_shift (rtx operands[])
return 0;
gcc_assert ((REG_P (operands[0]))
- || (GET_CODE (operands[0]) == SUBREG)
+ || (SUBREG_P (operands[0]))
|| (REG_P (operands[1]))
- || (GET_CODE (operands[1]) == SUBREG));
+ || (SUBREG_P (operands[1])));
/* Shift by zero -- copy regs if necessary. */
if (operands[2] == const0_rtx
@@ -3594,7 +3594,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
rtx comp_reg = gen_reg_rtx (SImode);
rtx condition;
- gcc_assert ((REG_P (cmp_op0)) || (GET_CODE (cmp_op0) == SUBREG));
+ gcc_assert ((REG_P (cmp_op0)) || (SUBREG_P (cmp_op0)));
/* If comparing against zero, just test source reg. */
if (cmp_op1 == const0_rtx)
@@ -3631,7 +3631,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
rtx condition;
gcc_assert ((REG_P (cmp_op0))
- || (GET_CODE (cmp_op0) == SUBREG));
+ || (SUBREG_P (cmp_op0)));
/* If comparing against zero, just test source reg. */
if (cmp_op1 == const0_rtx)
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index e72e0d57a97..4730c75ec5f 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -2480,7 +2480,7 @@ mips_regno_mode_ok_for_base_p (int regno, machine_mode mode,
static bool
mips_valid_base_register_p (rtx x, machine_mode mode, bool strict_p)
{
- if (!strict_p && GET_CODE (x) == SUBREG)
+ if (!strict_p && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -4480,7 +4480,7 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code,
if (outer_code == SET
&& ISA_HAS_BADDU
&& (GET_CODE (XEXP (x, 0)) == TRUNCATE
- || GET_CODE (XEXP (x, 0)) == SUBREG)
+ || SUBREG_P (XEXP (x, 0)))
&& GET_MODE (XEXP (x, 0)) == QImode
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
{
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index 8fdd1c5adf6..5d5bc734898 100644
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -1335,7 +1335,7 @@ mn10300_preferred_reload_class (rtx x, reg_class_t rclass)
else if (MEM_P (x)
|| (REG_P (x)
&& !HARD_REGISTER_P (x))
- || (GET_CODE (x) == SUBREG
+ || (SUBREG_P (x)
&& REG_P (SUBREG_REG (x))
&& !HARD_REGISTER_P (SUBREG_REG (x))))
return LIMIT_RELOAD_CLASS (GET_MODE (x), rclass);
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
index b36c8f5e38d..6a75b967a27 100644
--- a/gcc/config/mn10300/mn10300.h
+++ b/gcc/config/mn10300/mn10300.h
@@ -510,7 +510,7 @@ struct cum_arg
#define RTX_OK_FOR_BASE_P(X, strict) \
((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X), \
(strict))) \
- || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \
+ || (SUBREG_P (X) && REG_P (SUBREG_REG (X)) \
&& REGNO_STRICT_OK_FOR_BASE_P (REGNO (SUBREG_REG (X)), \
(strict))))
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index d28023b339f..40796b45883 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -3180,7 +3180,7 @@ msp430_subreg (machine_mode mode, rtx r, machine_mode omode, int byte)
{
rtx rv;
- if (GET_CODE (r) == SUBREG
+ if (SUBREG_P (r)
&& SUBREG_BYTE (r) == 0)
{
rtx ireg = SUBREG_REG (r);
diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md
index b516ec15462..e2aef5bd636 100644
--- a/gcc/config/msp430/msp430.md
+++ b/gcc/config/msp430/msp430.md
@@ -756,7 +756,7 @@
(match_operand:HI 2 "general_operand")))]
""
{
- if ((GET_CODE (operands[1]) == SUBREG
+ if ((SUBREG_P (operands[1])
&& REG_P (XEXP (operands[1], 0)))
|| MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
@@ -844,7 +844,7 @@
(match_operand:HI 2 "general_operand")))]
""
{
- if ((GET_CODE (operands[1]) == SUBREG
+ if ((SUBREG_P (operands[1])
&& REG_P (XEXP (operands[1], 0)))
|| MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
@@ -945,7 +945,7 @@
(match_operand:HI 2 "general_operand")))]
""
{
- if ((GET_CODE (operands[1]) == SUBREG
+ if ((SUBREG_P (operands[1])
&& REG_P (XEXP (operands[1], 0)))
|| MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
diff --git a/gcc/config/nds32/nds32-pipelines-auxiliary.c b/gcc/config/nds32/nds32-pipelines-auxiliary.c
index 09ad3d59af3..f205bcdff43 100644
--- a/gcc/config/nds32/nds32-pipelines-auxiliary.c
+++ b/gcc/config/nds32/nds32-pipelines-auxiliary.c
@@ -248,7 +248,7 @@ extract_nth_ls2_access_reg (rtx_insn *insn, int n)
gcc_unreachable ();
}
- gcc_assert (REG_P (reg) || GET_CODE (reg) == SUBREG);
+ gcc_assert (REG_P (reg) || SUBREG_P (reg));
switch (GET_MODE (reg))
{
@@ -332,7 +332,7 @@ movd44_even_dep_p (rtx_insn *insn, rtx def_reg)
{
return rtx_equal_p (def_reg, use_rtx);
}
- else if (GET_CODE (def_reg) == SUBREG
+ else if (SUBREG_P (def_reg)
&& GET_MODE (def_reg) == SImode
&& rtx_equal_p (SUBREG_REG (def_reg), use_rtx))
{
@@ -362,8 +362,8 @@ wext_odd_dep_p (rtx insn, rtx def_reg)
if (GET_MODE (def_reg) == DImode)
return reg_overlap_p (def_reg, use_reg);
- gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
- gcc_assert (REG_P (use_reg) || GET_CODE (use_reg) == SUBREG);
+ gcc_assert (REG_P (def_reg) || SUBREG_P (def_reg));
+ gcc_assert (REG_P (use_reg) || SUBREG_P (use_reg));
if (REG_P (def_reg))
{
@@ -378,12 +378,12 @@ wext_odd_dep_p (rtx insn, rtx def_reg)
return true;
}
- if (GET_CODE (def_reg) == SUBREG)
+ if (SUBREG_P (def_reg))
{
if (!reg_overlap_p (def_reg, use_reg))
return false;
- if (GET_CODE (use_reg) == SUBREG)
+ if (SUBREG_P (use_reg))
return true;
if (!TARGET_BIG_ENDIAN)
@@ -1200,7 +1200,7 @@ nds32_n7_last_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return n7_consumed_by_ii_dep_p (consumer, last_def_reg);
}
@@ -1298,7 +1298,7 @@ nds32_n8_last_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return n8_consumed_by_addr_in_p (consumer, last_def_reg);
}
@@ -1320,7 +1320,7 @@ nds32_n8_last_load_two_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
return false;
gcc_assert (REG_P (last_two_def_reg)
- || GET_CODE (last_two_def_reg) == SUBREG);
+ || SUBREG_P (last_two_def_reg));
return n8_consumed_by_addr_in_p (consumer, last_two_def_reg);
}
@@ -1340,7 +1340,7 @@ nds32_n8_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return n8_consumed_by_ex_p (consumer, last_def_reg);
}
@@ -1377,7 +1377,7 @@ nds32_e8_ex_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
rtx dest = SET_DEST (PATTERN (producer));
rtx src = SET_SRC (PATTERN (producer));
- if ((REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if ((REG_P (dest) || SUBREG_P (dest))
&& (CONST_INT_P (src) || GET_CODE (src) == HIGH))
return false;
}
@@ -1428,7 +1428,7 @@ nds32_e8_last_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return e8_consumed_by_addr_in_p (consumer, last_def_reg);
}
@@ -1441,7 +1441,7 @@ nds32_e8_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return e8_consumed_by_ex_p (consumer, last_def_reg);
}
@@ -1747,7 +1747,7 @@ nds32_n13_load_to_e1_p (rtx_insn *producer, rtx_insn *consumer)
rtx def_reg = SET_DEST (PATTERN (producer));
gcc_assert (get_attr_type (producer) == TYPE_LOAD);
- gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
+ gcc_assert (REG_P (def_reg) || SUBREG_P (def_reg));
return n13_consumed_by_e1_dep_p (consumer, def_reg);
}
@@ -1759,7 +1759,7 @@ nds32_n13_load_to_e2_p (rtx_insn *producer, rtx_insn *consumer)
rtx def_reg = SET_DEST (PATTERN (producer));
gcc_assert (get_attr_type (producer) == TYPE_LOAD);
- gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
+ gcc_assert (REG_P (def_reg) || SUBREG_P (def_reg));
return n13_consumed_by_e2_dep_p (consumer, def_reg);
}
diff --git a/gcc/config/nds32/nds32-utils.c b/gcc/config/nds32/nds32-utils.c
index 96ee791de54..327636bbd55 100644
--- a/gcc/config/nds32/nds32-utils.c
+++ b/gcc/config/nds32/nds32-utils.c
@@ -476,8 +476,8 @@ movd44_insn_p (rtx_insn *insn)
rtx src = SET_SRC (body);
rtx dest = SET_DEST (body);
- if ((REG_P (src) || GET_CODE (src) == SUBREG)
- && (REG_P (dest) || GET_CODE (dest) == SUBREG))
+ if ((REG_P (src) || SUBREG_P (src))
+ && (REG_P (dest) || SUBREG_P (dest)))
return true;
return false;
@@ -495,7 +495,7 @@ extract_movd44_odd_reg (rtx_insn *insn)
rtx def_reg = SET_DEST (PATTERN (insn));
machine_mode mode;
- gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
+ gcc_assert (REG_P (def_reg) || SUBREG_P (def_reg));
switch (GET_MODE (def_reg))
{
case E_DImode:
diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md
index 1e5f8decada..68ad1029387 100644
--- a/gcc/config/nds32/nds32.md
+++ b/gcc/config/nds32/nds32.md
@@ -216,7 +216,7 @@
DONE;
}
- if ((REG_P (operands[0]) || GET_CODE (operands[0]) == SUBREG)
+ if ((REG_P (operands[0]) || SUBREG_P (operands[0]))
&& SYMBOLIC_CONST_P (operands[1]))
{
if (TARGET_ICT_MODEL_LARGE
diff --git a/gcc/config/nds32/predicates.md b/gcc/config/nds32/predicates.md
index 9983eb4c409..6049c5c1b15 100644
--- a/gcc/config/nds32/predicates.md
+++ b/gcc/config/nds32/predicates.md
@@ -141,7 +141,7 @@
(match_operand 0 "nds32_reg_constant_operand")
{
return REG_P (op)
- || GET_CODE (op) == SUBREG
+ || SUBREG_P (op)
|| satisfies_constraint_Izeb (op)
|| satisfies_constraint_Izeh (op)
|| satisfies_constraint_Ixls (op)
@@ -157,7 +157,7 @@
(match_operand 0 "nds32_reg_constant_operand")
{
return REG_P (op)
- || GET_CODE (op) == SUBREG
+ || SUBREG_P (op)
|| satisfies_constraint_Iu15 (op)
|| satisfies_constraint_Ie15 (op);
})
@@ -166,7 +166,7 @@
(match_operand 0 "nds32_reg_constant_operand")
{
return REG_P (op)
- || GET_CODE (op) == SUBREG
+ || SUBREG_P (op)
|| satisfies_constraint_Iu15 (op)
|| satisfies_constraint_It15 (op);
})
@@ -174,7 +174,7 @@
(define_predicate "nds32_general_register_operand"
(match_code "reg,subreg")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return (REG_P (op)
diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c
index 6893ebb1528..74c80bbd1e3 100644
--- a/gcc/config/nios2/nios2.c
+++ b/gcc/config/nios2/nios2.c
@@ -2133,7 +2133,7 @@ nios2_valid_addr_offset_p (rtx offset)
static bool
nios2_valid_addr_expr_p (rtx base, rtx offset, bool strict_p)
{
- if (!strict_p && GET_CODE (base) == SUBREG)
+ if (!strict_p && SUBREG_P (base))
base = SUBREG_REG (base);
return (REG_P (base)
&& nios2_regno_ok_for_base_p (REGNO (base), strict_p)
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index 3107ea58818..39050c5e492 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -2308,9 +2308,9 @@ const char *
nvptx_output_mov_insn (rtx dst, rtx src)
{
machine_mode dst_mode = GET_MODE (dst);
- machine_mode dst_inner = (GET_CODE (dst) == SUBREG
+ machine_mode dst_inner = (SUBREG_P (dst)
? GET_MODE (XEXP (dst, 0)) : dst_mode);
- machine_mode src_inner = (GET_CODE (src) == SUBREG
+ machine_mode src_inner = (SUBREG_P (src)
? GET_MODE (XEXP (src, 0)) : dst_mode);
rtx sym = src;
@@ -2825,7 +2825,7 @@ nvptx_reorg_subreg (void)
for (int i = 0; i < recog_data.n_operands; i++)
{
rtx op = recog_data.operand[i];
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
continue;
rtx inner = SUBREG_REG (op);
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 6795fc393fd..cdd2e031bf7 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1169,7 +1169,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
if (GET_CODE (x) == PLUS
&& mem_shadd_or_shadd_rtx_p (XEXP (x, 0))
&& (OBJECT_P (XEXP (x, 1))
- || GET_CODE (XEXP (x, 1)) == SUBREG)
+ || SUBREG_P (XEXP (x, 1)))
&& GET_CODE (XEXP (x, 1)) != CONST)
{
/* If we were given a MULT, we must fix the constant
@@ -1670,7 +1670,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
operand0 = reg_equiv_mem (REGNO (operand0));
else if (scratch_reg
- && reload_in_progress && GET_CODE (operand0) == SUBREG
+ && reload_in_progress && SUBREG_P (operand0)
&& REG_P (SUBREG_REG (operand0))
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
{
@@ -1687,7 +1687,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
operand1 = reg_equiv_mem (REGNO (operand1));
else if (scratch_reg
- && reload_in_progress && GET_CODE (operand1) == SUBREG
+ && reload_in_progress && SUBREG_P (operand1)
&& REG_P (SUBREG_REG (operand1))
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
{
@@ -1716,12 +1716,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
if (scratch_reg
&& FP_REG_P (operand0)
&& (MEM_P (operand1)
- || (GET_CODE (operand1) == SUBREG
+ || (SUBREG_P (operand1)
&& MEM_P (XEXP (operand1, 0)))))
{
rtx op1 = operand1;
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = XEXP (op1, 0);
if (reg_plus_base_memory_operand (op1, GET_MODE (op1)))
@@ -1767,12 +1767,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
else if (scratch_reg
&& FP_REG_P (operand1)
&& (MEM_P (operand0)
- || (GET_CODE (operand0) == SUBREG
+ || (SUBREG_P (operand0)
&& MEM_P (XEXP (operand0, 0)))))
{
rtx op0 = operand0;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = XEXP (op0, 0);
if (reg_plus_base_memory_operand (op0, GET_MODE (op0)))
@@ -6110,7 +6110,7 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
/* Profiling showed the PA port spends about 1.3% of its compilation
time in true_regnum from calls inside pa_secondary_reload_class. */
- if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
+ if (regno >= FIRST_PSEUDO_REGISTER || SUBREG_P (x))
regno = true_regnum (x);
/* Handle reloads for floating point loads and stores. */
@@ -10546,7 +10546,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool strict)
{
rtx y = XEXP (x, 0);
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
y = SUBREG_REG (y);
if (REG_P (y)
diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md
index 903fa82b858..5fd0279c9fa 100644
--- a/gcc/config/pa/predicates.md
+++ b/gcc/config/pa/predicates.md
@@ -224,7 +224,7 @@
return false;
/* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
- if (reload_completed && GET_CODE (op) == SUBREG)
+ if (reload_completed && SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -243,7 +243,7 @@
return false;
/* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
- if (reload_completed && GET_CODE (op) == SUBREG)
+ if (reload_completed && SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -308,7 +308,7 @@
return true;
/* Extract CONST_INT operand. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
op = XEXP (op, 0);
op = REG_P (XEXP (op, 0)) ? XEXP (op, 1) : XEXP (op, 0);
@@ -345,7 +345,7 @@
return true;
/* Extract CONST_INT operand. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
op = XEXP (op, 0);
op = REG_P (XEXP (op, 0)) ? XEXP (op, 1) : XEXP (op, 0);
@@ -409,7 +409,7 @@
if (GET_MODE (op) != mode)
return false;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -440,7 +440,7 @@
if (GET_MODE (op) != mode)
return false;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -464,7 +464,7 @@
(define_predicate "nonsymb_mem_operand"
(match_code "subreg,mem")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -603,7 +603,7 @@
(define_predicate "symbolic_memory_operand"
(match_code "subreg,mem")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!MEM_P (op))
return false;
diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md
index a14c77373fc..eae67483f63 100644
--- a/gcc/config/pru/predicates.md
+++ b/gcc/config/pru/predicates.md
@@ -70,7 +70,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 0;
@@ -90,7 +90,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 0;
@@ -110,7 +110,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 0;
diff --git a/gcc/config/pru/pru.c b/gcc/config/pru/pru.c
index 971428e65bc..ead4c3b320f 100644
--- a/gcc/config/pru/pru.c
+++ b/gcc/config/pru/pru.c
@@ -1410,9 +1410,9 @@ pru_get_ctable_base_offset (unsigned HOST_WIDE_INT caddr)
static bool
pru_valid_addr_expr_p (machine_mode mode, rtx base, rtx offset, bool strict_p)
{
- if (!strict_p && GET_CODE (base) == SUBREG)
+ if (!strict_p && SUBREG_P (base))
base = SUBREG_REG (base);
- if (!strict_p && GET_CODE (offset) == SUBREG)
+ if (!strict_p && SUBREG_P (offset))
offset = SUBREG_REG (offset);
if (REG_P (base)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index ca868a2ddca..c03f5b1e66c 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -689,7 +689,7 @@ riscv_regno_mode_ok_for_base_p (int regno,
static bool
riscv_valid_base_register_p (rtx x, machine_mode mode, bool strict_p)
{
- if (!strict_p && GET_CODE (x) == SUBREG)
+ if (!strict_p && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -2121,11 +2121,11 @@ riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1)
is a constant or has already been sign-extended also. */
if (unsigned_condition (code) == code
&& (GET_MODE (*op0) == QImode
- && ! (GET_CODE (*op0) == SUBREG
+ && ! (SUBREG_P (*op0)
&& SUBREG_PROMOTED_VAR_P (*op0)
&& SUBREG_PROMOTED_SIGNED_P (*op0)
&& (CONST_INT_P (*op1)
- || (GET_CODE (*op1) == SUBREG
+ || (SUBREG_P (*op1)
&& SUBREG_PROMOTED_VAR_P (*op1)
&& SUBREG_PROMOTED_SIGNED_P (*op1))))))
{
diff --git a/gcc/config/rl78/rl78-expand.md b/gcc/config/rl78/rl78-expand.md
index 4b76101c1cb..3706a8c01f6 100644
--- a/gcc/config/rl78/rl78-expand.md
+++ b/gcc/config/rl78/rl78-expand.md
@@ -34,14 +34,14 @@
into a bitfield, or a packed ordinary field. We can handle this
provided that the destination is a register. If not, then load the
source into a register first. */
- if (GET_CODE (operands[1]) == SUBREG
+ if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
&& ! REG_P (operands[0]))
operands[1] = copy_to_mode_reg (QImode, operands[1]);
/* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))).
cf. g++.dg/abi/packed.C. */
- if (GET_CODE (operands[1]) == SUBREG
+ if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == CONST
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS
&& GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF
@@ -65,11 +65,11 @@
/* FIXME: Not sure how GCC can generate (SUBREG (SYMBOL_REF)),
but it does. Since this makes no sense, reject it here. */
- if (GET_CODE (operands[1]) == SUBREG
+ if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
FAIL;
/* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))). */
- if (GET_CODE (operands[1]) == SUBREG
+ if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == CONST
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS
&& GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF)
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index f3f7ecb4b22..779c94e038f 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -951,7 +951,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
*base = XEXP (x, 0);
x = XEXP (x, 1);
- if (GET_CODE (*base) == SUBREG)
+ if (SUBREG_P (*base))
{
if (GET_MODE (*base) == HImode
&& GET_MODE (XEXP (*base, 0)) == SImode
diff --git a/gcc/config/rl78/rl78.h b/gcc/config/rl78/rl78.h
index a04f7b3fe0e..341e5404ad2 100644
--- a/gcc/config/rl78/rl78.h
+++ b/gcc/config/rl78/rl78.h
@@ -454,7 +454,7 @@ typedef unsigned int CUMULATIVE_ARGS;
#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
/* This is a version of REG_P that also returns TRUE for SUBREGs. */
-#define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
+#define RL78_REG_P(rtl) (REG_P (rtl) || SUBREG_P (rtl))
/* Like REG_P except that this macro is true for SET expressions. */
#define SET_P(rtl) (GET_CODE (rtl) == SET)
diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h
index 672e087cd13..9846ad017c5 100644
--- a/gcc/config/rx/rx.h
+++ b/gcc/config/rx/rx.h
@@ -294,12 +294,12 @@ enum reg_class
((STRICT) ? \
( (REG_P (X) \
&& REGNO_IN_RANGE (REGNO (X), 0, 15)) \
- || (GET_CODE (X) == SUBREG \
+ || (SUBREG_P (X) \
&& REG_P (SUBREG_REG (X)) \
&& REGNO_IN_RANGE (REGNO (SUBREG_REG (X)), 0, 15))) \
: \
( (REG_P (X) \
- || (GET_CODE (X) == SUBREG \
+ || (SUBREG_P (X) \
&& REG_P (SUBREG_REG (X))))))
@@ -615,7 +615,7 @@ typedef unsigned int CUMULATIVE_ARGS;
#define JUMP_TABLES_IN_TEXT_SECTION (TARGET_PID || flag_pic)
/* This is a version of REG_P that also returns TRUE for SUBREGs. */
-#define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
+#define RX_REG_P(rtl) (REG_P (rtl) || SUBREG_P (rtl))
/* Like REG_P except that this macro is true for SET expressions. */
#define SET_P(rtl) (GET_CODE (rtl) == SET)
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index aec2de30219..b05e8ed6ed0 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -65,7 +65,7 @@
/* Just like memory_operand, allow (subreg (mem ...))
after reload. */
if (reload_completed
- && GET_CODE (op) == SUBREG
+ && SUBREG_P (op)
&& GET_CODE (SUBREG_REG (op)) == MEM)
op = SUBREG_REG (op);
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index a61c7d5ed79..d38cf3aad12 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -1647,7 +1647,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
rtx mask = XEXP (*op0, 1);
/* Ignore paradoxical SUBREGs if all extra bits are masked out. */
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
&& (GET_MODE_SIZE (GET_MODE (inner))
>= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
@@ -2666,7 +2666,7 @@ s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
/* Widen operands if required. */
if (mode != wmode)
{
- if (GET_CODE (dst) == SUBREG
+ if (SUBREG_P (dst)
&& (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
dst = tem;
else if (REG_P (dst))
@@ -2674,13 +2674,13 @@ s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
else
dst = gen_reg_rtx (wmode);
- if (GET_CODE (src1) == SUBREG
+ if (SUBREG_P (src1)
&& (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
src1 = tem;
else if (GET_MODE (src1) != VOIDmode)
src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
- if (GET_CODE (src2) == SUBREG
+ if (SUBREG_P (src2)
&& (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
src2 = tem;
else if (GET_MODE (src2) != VOIDmode)
@@ -3116,7 +3116,7 @@ s390_decompose_addrstyle_without_index (rtx op, rtx *base,
off = XEXP (op, 1);
op = XEXP (op, 0);
}
- while (op && GET_CODE (op) == SUBREG)
+ while (op && SUBREG_P (op))
op = SUBREG_REG (op);
if (op && !REG_P (op))
@@ -3155,7 +3155,7 @@ bool
s390_valid_shift_count (rtx op, HOST_WIDE_INT implicit_mask)
{
/* Strip subreg. */
- while (GET_CODE (op) == SUBREG && subreg_lowpart_p (op))
+ while (SUBREG_P (op) && subreg_lowpart_p (op))
op = XEXP (op, 0);
/* Check for an and with proper constant. */
@@ -3164,7 +3164,7 @@ s390_valid_shift_count (rtx op, HOST_WIDE_INT implicit_mask)
rtx op1 = XEXP (op, 0);
rtx imm = XEXP (op, 1);
- if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
+ if (SUBREG_P (op1) && subreg_lowpart_p (op1))
op1 = XEXP (op1, 0);
if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
@@ -7513,7 +7513,7 @@ print_shift_count_operand (FILE *file, rtx op)
if (!s390_valid_shift_count (op, 0))
gcc_unreachable ();
- while (op && GET_CODE (op) == SUBREG)
+ while (op && SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == AND)
@@ -8208,7 +8208,7 @@ addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn)
target = SET_DEST (dep_rtx);
if (GET_CODE (target) == STRICT_LOW_PART)
target = XEXP (target, 0);
- while (GET_CODE (target) == SUBREG)
+ while (SUBREG_P (target))
target = SUBREG_REG (target);
if (REG_P (target))
@@ -9379,7 +9379,7 @@ s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *d
unsigned int i, regno;
machine_mode mode = GET_MODE (setreg);
- if (GET_CODE (setreg) == SUBREG)
+ if (SUBREG_P (setreg))
{
rtx inner = SUBREG_REG (setreg);
if (!GENERAL_REG_P (inner) && !FP_REG_P (inner))
diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md
index c22f3e2e31e..4b19143d90e 100644
--- a/gcc/config/sh/predicates.md
+++ b/gcc/config/sh/predicates.md
@@ -28,7 +28,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 1;
@@ -49,11 +49,11 @@
return register_operand (XEXP (op, 0), VOIDmode);
#endif
if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
- && GET_CODE (op) == SUBREG
+ && SUBREG_P (op)
&& GET_MODE (SUBREG_REG (op)) == DImode
&& GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
&& GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
- && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
+ && !SUBREG_P (XEXP (SUBREG_REG (op), 0)))
return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
return 0;
})
@@ -121,7 +121,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 1;
@@ -199,7 +199,7 @@
if (reload_completed && GET_CODE (op) == TRUNCATE)
return arith_operand (op, mode);
- if (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))
+ if (MEM_P (op) || (SUBREG_P (op) && MEM_P (SUBREG_REG (op))))
return general_movsrc_operand (op, mode);
return nonimmediate_operand (op, mode);
@@ -300,7 +300,7 @@
}
if (mode == GET_MODE (op)
- && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
+ && (MEM_P (op) || (SUBREG_P (op) && MEM_P (SUBREG_REG (op)))))
{
rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
rtx x = XEXP (mem_rtx, 0);
@@ -310,11 +310,11 @@
rtx y = XEXP (x, 0);
if (! REG_P (y)
- && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))
+ && ! (SUBREG_P (y) && REG_P (SUBREG_REG (y))))
return false;
y = XEXP (x, 1);
if (! REG_P (y)
- && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))
+ && ! (SUBREG_P (y) && REG_P (SUBREG_REG (y)))
&& ! CONST_INT_P (y))
return false;
}
@@ -385,7 +385,7 @@
return 0;
if (mode == GET_MODE (op)
- && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
+ && (MEM_P (op) || (SUBREG_P (op) && MEM_P (SUBREG_REG (op)))))
{
rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
rtx x = XEXP (mem_rtx, 0);
@@ -395,11 +395,11 @@
rtx y = XEXP (x, 0);
if (! REG_P (y)
- && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))
+ && ! (SUBREG_P (y) && REG_P (SUBREG_REG (y))))
return false;
y = XEXP (x, 1);
if (! REG_P (y)
- && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))
+ && ! (SUBREG_P (y) && REG_P (SUBREG_REG (y)))
&& ! CONST_INT_P (y))
return false;
}
@@ -658,7 +658,7 @@
case SIGN_EXTEND:
if (REG_P (XEXP (op, 0)) && REGNO (XEXP (op, 0)) == T_REG)
return true;
- return GET_CODE (XEXP (op, 0)) == SUBREG
+ return SUBREG_P (XEXP (op, 0))
&& REG_P (SUBREG_REG (XEXP (op, 0)))
&& REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG;
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 3e2ffcff0f1..1a2d110c2ae 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -1194,7 +1194,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
held in general purpose registers, that won't work with memory -
neither for fp registers, since the frxx names are used. */
case 'R':
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
{
regno = true_regnum (x);
regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET;
@@ -1221,7 +1221,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
}
break;
case 'S':
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
{
regno = true_regnum (x);
regno += FP_REGISTER_P (regno) ? 0 : SH_REG_MSW_OFFSET;
@@ -1389,7 +1389,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
machine_mode inner_mode;
/* We might see SUBREGs with vector mode registers inside. */
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& (GET_MODE_SIZE (GET_MODE (inner))
== GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
&& subreg_lowpart_p (inner))
@@ -1400,7 +1400,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
goto default_output;
}
inner_mode = GET_MODE (inner);
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& (GET_MODE_SIZE (GET_MODE (inner))
< GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
&& REG_P (SUBREG_REG (inner)))
@@ -3180,7 +3180,7 @@ addsubcosts (rtx x)
/* Adding a register is a single cycle insn. */
if (REG_P (XEXP (x, 1))
- || GET_CODE (XEXP (x, 1)) == SUBREG)
+ || SUBREG_P (XEXP (x, 1)))
return 1 * cost_scale;
/* Likewise for small constants. */
@@ -3711,7 +3711,7 @@ gen_ashift_hi (int type, int n, rtx reg)
sign extension works out correctly. */
{
int offset = 0;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
offset = SUBREG_BYTE (reg);
reg = SUBREG_REG (reg);
@@ -6208,7 +6208,7 @@ sh_reorg (void)
int offset = 0;
mode = HImode;
- while (GET_CODE (dst) == SUBREG)
+ while (SUBREG_P (dst))
{
offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
GET_MODE (SUBREG_REG (dst)),
@@ -11391,7 +11391,7 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
and that has to be added to the final address. At this point we don't
know the cumulative displacement so we assume the worst case. */
if ((mode == QImode || mode == HImode) && rclass != R0_REGS
- && GET_CODE (x) == SUBREG && true_regnum (x) == -1)
+ && SUBREG_P (x) && true_regnum (x) == -1)
return R0_REGS;
return NO_REGS;
@@ -11940,7 +11940,7 @@ sh_try_omit_signzero_extend (rtx extended_op, rtx_insn* insn)
{
if (REG_P (extended_op))
extended_op = extended_op;
- else if (GET_CODE (extended_op) == SUBREG && REG_P (SUBREG_REG (extended_op)))
+ else if (SUBREG_P (extended_op) && REG_P (SUBREG_REG (extended_op)))
extended_op = SUBREG_REG (extended_op);
else
return NULL_RTX;
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 37bfc02de98..f753c611aaf 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1421,7 +1421,7 @@ extern bool current_function_interrupt;
#define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
- || (GET_CODE (X) == SUBREG \
+ || (SUBREG_P (X) \
&& REG_P (SUBREG_REG (X)) \
&& REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
@@ -1430,7 +1430,7 @@ extern bool current_function_interrupt;
outside the class. */
#define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
- || (GET_CODE (X) == SUBREG \
+ || (SUBREG_P (X) \
&& REG_P (SUBREG_REG (X)) \
&& SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index ed70e344dfa..86a27e24788 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -5682,7 +5682,7 @@
mem = operands[1];
store_p = 0;
}
- if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
+ if (SUBREG_P (mem) && SUBREG_BYTE (mem) == 0)
mem = SUBREG_REG (mem);
if (MEM_P (mem))
{
@@ -5695,7 +5695,7 @@
rtx reg0 = gen_rtx_REG (Pmode, 0);
rtx regop = operands[store_p], word0 ,word1;
- if (GET_CODE (regop) == SUBREG)
+ if (SUBREG_P (regop))
alter_subreg (®op, true);
if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
offset = 2;
@@ -10781,7 +10781,7 @@
(match_operand:SF 2 "general_movsrc_operand" ""))]
"TARGET_SH1 && REGNO (operands[0]) == 0
&& ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
- || (GET_CODE (operands[2]) == SUBREG
+ || (SUBREG_P (operands[2])
&& REGNO (SUBREG_REG (operands[2])) < 16))
&& reg_unused_after (operands[0], insn)"
"mov.l %2,@(%0,%1)")
@@ -10794,7 +10794,7 @@
(mem:SF (match_dup 0)))]
"TARGET_SH1 && REGNO (operands[0]) == 0
&& ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
- || (GET_CODE (operands[2]) == SUBREG
+ || (SUBREG_P (operands[2])
&& REGNO (SUBREG_REG (operands[2])) < 16))
&& reg_unused_after (operands[0], insn)"
"mov.l @(%0,%1),%2")
@@ -10807,7 +10807,7 @@
"TARGET_SH2E && REGNO (operands[0]) == 0
&& ((REG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
- || (GET_CODE (operands[2]) == SUBREG
+ || (SUBREG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
&& reg_unused_after (operands[0], insn)"
"fmov{.s|} %2,@(%0,%1)")
@@ -10821,7 +10821,7 @@
"TARGET_SH2E && REGNO (operands[0]) == 0
&& ((REG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
- || (GET_CODE (operands[2]) == SUBREG
+ || (SUBREG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
&& reg_unused_after (operands[0], insn)"
"fmov{.s|} @(%0,%1),%2")
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index 09c3312f955..d947736e933 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -222,7 +222,7 @@
(define_predicate "fp_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op); /* Possibly a MEM */
return REG_P (op) && SPARC_FP_REG_P (REGNO (op));
})
@@ -411,7 +411,7 @@
return true;
/* If this is a SUBREG, look inside so that we handle paradoxical ones. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
/* Check for valid MEM forms. */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index df371584f9e..523f2851d31 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2958,7 +2958,7 @@ sparc_emit_set_const64 (rtx op0, rtx op1)
/* Sanity check that we know what we are working with. */
gcc_assert (TARGET_ARCH64
- && (GET_CODE (op0) == SUBREG
+ && (SUBREG_P (op0)
|| (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
if (! can_create_pseudo_p ())
@@ -3490,8 +3490,8 @@ emit_scc_insn (rtx operands[])
back to the easy case. */
if (code == GTU || code == LEU)
{
- if ((REG_P (x) || GET_CODE (x) == SUBREG)
- && (REG_P (y) || GET_CODE (y) == SUBREG))
+ if ((REG_P (x) || SUBREG_P (x))
+ && (REG_P (y) || SUBREG_P (y)))
{
tem = x;
x = y;
@@ -4016,7 +4016,7 @@ eligible_for_restore_insn (rtx trial, bool return_p)
VIS3 is enabled, we have to catch this case. We can allow such
moves when doing a 'return' however. */
src_reg = src;
- if (GET_CODE (src_reg) == SUBREG)
+ if (SUBREG_P (src_reg))
src_reg = SUBREG_REG (src_reg);
if (REG_P (src_reg)
&& SPARC_FP_REG_P (REGNO (src_reg)))
@@ -4480,7 +4480,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
{
rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
- if (REG_P (addr) || GET_CODE (addr) == SUBREG)
+ if (REG_P (addr) || SUBREG_P (addr))
rs1 = addr;
else if (GET_CODE (addr) == PLUS)
{
@@ -4490,9 +4490,9 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
/* Canonicalize. REG comes first, if there are no regs,
LO_SUM comes first. */
if (!REG_P (rs1)
- && GET_CODE (rs1) != SUBREG
+ && !SUBREG_P (rs1)
&& (REG_P (rs2)
- || GET_CODE (rs2) == SUBREG
+ || SUBREG_P (rs2)
|| (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
{
rs1 = XEXP (addr, 1);
@@ -4502,21 +4502,21 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
if ((flag_pic == 1
&& sparc_pic_register_p (rs1)
&& !REG_P (rs2)
- && GET_CODE (rs2) != SUBREG
+ && !SUBREG_P (rs2)
&& GET_CODE (rs2) != LO_SUM
&& GET_CODE (rs2) != MEM
&& !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
&& (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
&& (!CONST_INT_P (rs2) || SMALL_INT (rs2)))
|| ((REG_P (rs1)
- || GET_CODE (rs1) == SUBREG)
+ || SUBREG_P (rs1))
&& RTX_OK_FOR_OFFSET_P (rs2, mode)))
{
imm1 = rs2;
rs2 = NULL;
}
- else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
- && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
+ else if ((REG_P (rs1) || SUBREG_P (rs1))
+ && (REG_P (rs2) || SUBREG_P (rs2)))
{
/* We prohibit REG + REG for TFmode when there are no quad move insns
and we consequently need to split. We do this because REG+REG
@@ -4580,14 +4580,14 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
else
return 0;
- if (GET_CODE (rs1) == SUBREG)
+ if (SUBREG_P (rs1))
rs1 = SUBREG_REG (rs1);
if (!REG_P (rs1))
return 0;
if (rs2)
{
- if (GET_CODE (rs2) == SUBREG)
+ if (SUBREG_P (rs2))
rs2 = SUBREG_REG (rs2);
if (!REG_P (rs2))
return 0;
@@ -9036,13 +9036,13 @@ sparc_split_reg_reg_legitimate (rtx reg1, rtx reg2)
/* Punt if we are here by mistake. */
gcc_assert (reload_completed);
- if (GET_CODE (reg1) == SUBREG)
+ if (SUBREG_P (reg1))
reg1 = SUBREG_REG (reg1);
if (!REG_P (reg1))
return 0;
const int regno1 = REGNO (reg1);
- if (GET_CODE (reg2) == SUBREG)
+ if (SUBREG_P (reg2))
reg2 = SUBREG_REG (reg2);
if (!REG_P (reg2))
return 0;
@@ -13403,7 +13403,7 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
if (FP_REG_CLASS_P (rclass)
&& (mode == HImode || mode == QImode)
&& (GET_CODE (x) == MEM
- || ((REG_P (x) || GET_CODE (x) == SUBREG)
+ || ((REG_P (x) || SUBREG_P (x))
&& true_regnum (x) == -1)))
return GENERAL_REGS;
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 26b7f808e82..0c003a2fdf2 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2133,7 +2133,7 @@ visl")
&& TARGET_ARCH32
&& ((REG_P (operands[0])
&& SPARC_INT_REG_P (REGNO (operands[0])))
- || (GET_CODE (operands[0]) == SUBREG
+ || (SUBREG_P (operands[0])
&& REG_P (SUBREG_REG (operands[0]))
&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
[(clobber (const_int 0))]
@@ -2579,7 +2579,7 @@ visl")
&& TARGET_ARCH32
&& ((REG_P (operands[0])
&& SPARC_INT_REG_P (REGNO (operands[0])))
- || (GET_CODE (operands[0]) == SUBREG
+ || (SUBREG_P (operands[0])
&& REG_P (SUBREG_REG (operands[0]))
&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
[(clobber (const_int 0))]
@@ -3031,7 +3031,7 @@ visl")
rtx shift_16 = GEN_INT (16);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (SImode);
@@ -3114,7 +3114,7 @@ visl")
rtx shift_48 = GEN_INT (48);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (DImode);
@@ -3300,7 +3300,7 @@ visl")
rtx shift_16 = GEN_INT (16);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (SImode);
@@ -3332,14 +3332,14 @@ visl")
int op1_subbyte = 0;
int op0_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (SImode);
op1_subbyte *= GET_MODE_SIZE (SImode);
operand1 = XEXP (operand1, 0);
}
- if (GET_CODE (operand0) == SUBREG)
+ if (SUBREG_P (operand0))
{
op0_subbyte = SUBREG_BYTE (operand0);
op0_subbyte /= GET_MODE_SIZE (SImode);
@@ -3371,7 +3371,7 @@ visl")
rtx shift_24 = GEN_INT (24);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (SImode);
@@ -3402,7 +3402,7 @@ visl")
rtx shift_56 = GEN_INT (56);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (DImode);
@@ -3433,7 +3433,7 @@ visl")
rtx shift_48 = GEN_INT (48);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (DImode);
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index e850c9ba40e..668a1950c9a 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -362,7 +362,7 @@ adjust_operand (rtx op, HOST_WIDE_INT * start)
machine_mode mode;
int op_size;
/* Strip any paradoxical SUBREG. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& (GET_MODE_BITSIZE (GET_MODE (op))
> GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op)))))
{
@@ -440,7 +440,7 @@ spu_expand_extv (rtx ops[], int unsignedp)
}
}
- else if (GET_CODE (src) == SUBREG)
+ else if (SUBREG_P (src))
{
rtx r = SUBREG_REG (src);
gcc_assert (REG_P (r) && SCALAR_INT_MODE_P (GET_MODE (r)));
@@ -3551,9 +3551,9 @@ spu_legitimate_address_p (machine_mode mode,
{
rtx op0 = XEXP (x, 0);
rtx op1 = XEXP (x, 1);
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = XEXP (op0, 0);
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = XEXP (op1, 0);
if (REG_P (op0)
&& INT_REG_OK_FOR_BASE_P (op0, reg_ok_strict)
@@ -4442,7 +4442,7 @@ expand_ea_mem (rtx mem, bool is_store)
int
spu_expand_mov (rtx * ops, machine_mode mode)
{
- if (GET_CODE (ops[0]) == SUBREG && !valid_subreg (ops[0]))
+ if (SUBREG_P (ops[0]) && !valid_subreg (ops[0]))
{
/* Perform the move in the destination SUBREG's inner mode. */
ops[0] = SUBREG_REG (ops[0]);
@@ -4451,7 +4451,7 @@ spu_expand_mov (rtx * ops, machine_mode mode)
gcc_assert (ops[1]);
}
- if (GET_CODE (ops[1]) == SUBREG && !valid_subreg (ops[1]))
+ if (SUBREG_P (ops[1]) && !valid_subreg (ops[1]))
{
rtx from = SUBREG_REG (ops[1]);
scalar_int_mode imode = int_mode_for_mode (GET_MODE (from)).require ();
@@ -4843,7 +4843,7 @@ spu_split_store (rtx * ops)
{
if (REG_P (ops[1]))
emit_insn (gen_spu_convert (reg, ops[1]));
- else if (GET_CODE (ops[1]) == SUBREG)
+ else if (SUBREG_P (ops[1]))
emit_insn (gen_spu_convert (reg, SUBREG_REG (ops[1])));
else
abort ();
@@ -5481,7 +5481,7 @@ spu_init_libfuncs (void)
rtx
spu_gen_subreg (machine_mode mode, rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (GET_MODE (x) == mode)
return x;
@@ -5662,7 +5662,7 @@ spu_builtin_splats (rtx ops[])
rtx reg = gen_reg_rtx (TImode);
rtx shuf;
if (!REG_P (ops[1])
- && GET_CODE (ops[1]) != SUBREG)
+ && !SUBREG_P (ops[1]))
ops[1] = force_reg (GET_MODE_INNER (mode), ops[1]);
switch (mode)
{
diff --git a/gcc/config/stormy16/predicates.md b/gcc/config/stormy16/predicates.md
index e5a653ac5a7..9f9edcb4b1b 100644
--- a/gcc/config/stormy16/predicates.md
+++ b/gcc/config/stormy16/predicates.md
@@ -67,7 +67,7 @@
return 0;
if (GET_CODE (op) == MEM)
op = XEXP (op, 0);
- else if (GET_CODE (op) == SUBREG
+ else if (SUBREG_P (op)
&& GET_CODE (XEXP (op, 0)) == MEM
&& !MEM_VOLATILE_P (XEXP (op, 0)))
op = XEXP (XEXP (op, 0), 0);
diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c
index bd551100183..9a2b744426f 100644
--- a/gcc/config/stormy16/stormy16.c
+++ b/gcc/config/stormy16/stormy16.c
@@ -482,7 +482,7 @@ xstormy16_secondary_reload_class (enum reg_class rclass,
/* This chip has the interesting property that only the first eight
registers can be moved to/from memory. */
if ((MEM_P (x)
- || ((GET_CODE (x) == SUBREG || REG_P (x))
+ || ((SUBREG_P (x) || REG_P (x))
&& (true_regnum (x) == -1
|| true_regnum (x) >= FIRST_PSEUDO_REGISTER)))
&& ! reg_class_subset_p (rclass, EIGHT_REGS))
@@ -732,7 +732,7 @@ xstormy16_split_move (machine_mode mode, rtx dest, rtx src)
gcc_assert (! MEM_P (dest) || ! MEM_P (src));
/* This case is very very bad after reload, so trap it now. */
- gcc_assert (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
+ gcc_assert (!SUBREG_P (dest) && !SUBREG_P (src));
/* The general idea is to copy by words, offsetting the source and
destination. Normally the least-significant word will be copied
@@ -828,8 +828,8 @@ xstormy16_split_move (machine_mode mode, rtx dest, rtx src)
MEM_VOLATILE_P (w_dest) = 1;
/* The simplify_subreg calls must always be able to simplify. */
- gcc_assert (GET_CODE (w_src) != SUBREG
- && GET_CODE (w_dest) != SUBREG);
+ gcc_assert (!SUBREG_P (w_src)
+ && !SUBREG_P (w_dest));
insn = emit_insn (gen_rtx_SET (w_dest, w_src));
if (auto_inc_reg_rtx)
@@ -876,7 +876,7 @@ xstormy16_expand_move (machine_mode mode, rtx dest, rtx src)
|| ! xstormy16_legitimate_address_p (mode, XEXP (dest, 0), 0))
&& ! xstormy16_below100_operand (dest, mode)
&& ! REG_P (src)
- && GET_CODE (src) != SUBREG)
+ && !SUBREG_P (src))
src = copy_to_mode_reg (mode, src);
/* Don't emit something we would immediately split. */
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index b6cf8115c13..26ab4889147 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -875,7 +875,7 @@ static bool
tilegx_legitimate_address_p (machine_mode ARG_UNUSED (mode), rtx x,
bool strict)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
switch (GET_CODE (x))
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index f2e24858970..2cf16edd86d 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -775,7 +775,7 @@ static bool
tilepro_legitimate_address_p (machine_mode ARG_UNUSED (mode), rtx x,
bool strict)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
switch (GET_CODE (x))
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index 201bed4bcdb..3412e69563b 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -688,7 +688,7 @@ v850_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
break;
case PLUS:
if (REG_P (XEXP (addr, 0))
- || GET_CODE (XEXP (addr, 0)) == SUBREG)
+ || SUBREG_P (XEXP (addr, 0)))
{
/* reg,foo */
v850_print_operand (file, XEXP (addr, 1), 0);
@@ -1300,11 +1300,11 @@ v850_reorg (void)
/* We might have (SUBREG (MEM)) here, so just get rid of the
subregs to make this code simpler. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& (GET_CODE (SUBREG_REG (dest)) == MEM
|| REG_P (SUBREG_REG (dest))))
alter_subreg (&dest, false);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& (GET_CODE (SUBREG_REG (src)) == MEM
|| REG_P (SUBREG_REG (src))))
alter_subreg (&src, false);
diff --git a/gcc/config/visium/predicates.md b/gcc/config/visium/predicates.md
index 1515abd968c..5547ec56444 100644
--- a/gcc/config/visium/predicates.md
+++ b/gcc/config/visium/predicates.md
@@ -47,7 +47,7 @@
(define_predicate "gpc_reg_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
op = SUBREG_REG (op);
if (!REG_P (op))
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index b2bc847b971..1621f4a6403 100644
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -1051,7 +1051,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
if (GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
out_reg = REGNO (dest);
@@ -1066,7 +1066,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
if (GET_CODE (memexpr) == PLUS)
{
memexpr = XEXP (memexpr, 0);
- if (GET_CODE (memexpr) == SUBREG)
+ if (SUBREG_P (memexpr))
in_reg = REGNO (SUBREG_REG (memexpr));
else
in_reg = REGNO (memexpr);
@@ -1078,7 +1078,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
{
if (GET_CODE (memexpr) == STRICT_LOW_PART)
memexpr = XEXP (memexpr, 0);
- if (GET_CODE (memexpr) == SUBREG)
+ if (SUBREG_P (memexpr))
memexpr = SUBREG_REG (memexpr);
in_reg = REGNO (memexpr);
@@ -1842,7 +1842,7 @@ visium_legitimate_address_p (machine_mode mode, rtx x, bool strict)
base = x;
/* Now check the base: it must be either a register or a subreg thereof. */
- if (GET_CODE (base) == SUBREG)
+ if (SUBREG_P (base))
base = SUBREG_REG (base);
if (!REG_P (base))
return false;
@@ -2124,7 +2124,7 @@ visium_split_double_move (rtx *operands, machine_mode mode)
{
rtx op = XEXP (operands[1], 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REG_P (op) && REGNO (op) == REGNO (operands[0]))
@@ -4305,7 +4305,7 @@ reg_or_subreg_regno (rtx op)
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
{
if (REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
regno = subreg_regno (op);
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index d5aad718e41..505b86397b9 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -477,7 +477,7 @@ xt_true_regnum (rtx x)
return reg_renumber[REGNO (x)];
return REGNO (x);
}
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
int base = xt_true_regnum (SUBREG_REG (x));
if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
@@ -580,7 +580,7 @@ constantpool_address_p (const_rtx addr)
int
constantpool_mem_p (rtx op)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == MEM)
return constantpool_address_p (XEXP (op, 0));
@@ -742,7 +742,7 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
cmp1 = force_reg (mode, cmp1);
}
}
- else if ((!REG_P (cmp1)) && (GET_CODE (cmp1) != SUBREG))
+ else if ((!REG_P (cmp1)) && (!SUBREG_P (cmp1)))
{
cmp1 = force_reg (mode, cmp1);
}
@@ -1118,7 +1118,7 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
static rtx
fixup_subreg_mem (rtx x)
{
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& REG_P (SUBREG_REG (x))
&& REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
{
@@ -1168,7 +1168,7 @@ xtensa_copy_incoming_a7 (rtx opnd)
/* The operand using a7 may come in a later instruction, so just return
the original operand if it doesn't use a7. */
reg = opnd;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
gcc_assert (SUBREG_BYTE (reg) == 0);
reg = SUBREG_REG (reg);
@@ -1831,7 +1831,7 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
&& ! xtensa_tls_referenced_p (addr))
return true;
- while (GET_CODE (addr) == SUBREG)
+ while (SUBREG_P (addr))
addr = SUBREG_REG (addr);
/* Allow base registers. */
@@ -1846,11 +1846,11 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
enum rtx_code code0;
enum rtx_code code1;
- while (GET_CODE (xplus0) == SUBREG)
+ while (SUBREG_P (xplus0))
xplus0 = SUBREG_REG (xplus0);
code0 = GET_CODE (xplus0);
- while (GET_CODE (xplus1) == SUBREG)
+ while (SUBREG_P (xplus1))
xplus1 = SUBREG_REG (xplus1);
code1 = GET_CODE (xplus1);
@@ -2369,7 +2369,7 @@ print_operand (FILE *file, rtx x, int letter)
switch (letter)
{
case 'D':
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
else
output_operand_lossage ("invalid %%D value");
@@ -2501,7 +2501,7 @@ print_operand (FILE *file, rtx x, int letter)
/* fall through */
default:
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
else if (GET_CODE (x) == MEM)
output_address (GET_MODE (x), XEXP (x, 0));
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 40af6056024..757ece341e6 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -862,7 +862,7 @@
}
else
{
- gcc_assert (GET_CODE (operands[1]) == SUBREG);
+ gcc_assert (SUBREG_P (operands[1]));
lit = SUBREG_REG (operands[1]);
word_off = SUBREG_BYTE (operands[1]) & ~(UNITS_PER_WORD - 1);
byte_off = SUBREG_BYTE (operands[1]) - word_off;
diff --git a/gcc/cse.c b/gcc/cse.c
index 7747986d637..afc6f50edbe 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -722,7 +722,7 @@ static int
notreg_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno)
{
scalar_int_mode int_mode, inner_mode;
- return ((GET_CODE (x) == SUBREG
+ return ((SUBREG_P (x)
&& REG_P (SUBREG_REG (x))
&& is_int_mode (mode, &int_mode)
&& is_int_mode (GET_MODE (SUBREG_REG (x)), &inner_mode)
@@ -1171,7 +1171,7 @@ insert_regs (rtx x, struct table_elt *classp, int modified)
not be accessible because its hash code will have changed. So assign
a quantity number now. */
- else if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))
+ else if (SUBREG_P (x) && REG_P (SUBREG_REG (x))
&& ! REGNO_QTY_VALID_P (REGNO (SUBREG_REG (x))))
{
insert_regs (SUBREG_REG (x), NULL, 0);
@@ -1984,7 +1984,7 @@ static void
invalidate_dest (rtx dest)
{
if (REG_P (dest)
- || GET_CODE (dest) == SUBREG
+ || SUBREG_P (dest)
|| MEM_P (dest))
invalidate (dest, VOIDmode);
else if (GET_CODE (dest) == STRICT_LOW_PART
@@ -2028,7 +2028,7 @@ remove_invalid_subreg_refs (unsigned int regno, poly_uint64 offset,
next = p->next_same_hash;
if (!REG_P (exp)
- && (GET_CODE (exp) != SUBREG
+ && (!SUBREG_P (exp)
|| !REG_P (SUBREG_REG (exp))
|| REGNO (SUBREG_REG (exp)) != regno
|| ranges_maybe_overlap_p (SUBREG_BYTE (exp),
@@ -2051,7 +2051,7 @@ rehash_using_reg (rtx x)
struct table_elt *p, *next;
unsigned hash;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
/* If X is not a register or if the register is known not to be in any
@@ -3811,7 +3811,7 @@ equiv_constant (rtx x)
if (x == 0 || CONSTANT_P (x))
return x;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
machine_mode mode = GET_MODE (x);
machine_mode imode = GET_MODE (SUBREG_REG (x));
@@ -4517,7 +4517,7 @@ canonicalize_insn (rtx_insn *insn, struct set **psets, int n_sets)
canon_reg (XEXP (dest, 2), insn), 1);
}
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -5066,7 +5066,7 @@ cse_insn (rtx_insn *insn)
looking for. */
if (paradoxical_subreg_p (p->exp)
&& ! (src != 0
- && GET_CODE (src) == SUBREG
+ && SUBREG_P (src)
&& GET_MODE (src) == GET_MODE (p->exp)
&& partial_subreg_p (GET_MODE (SUBREG_REG (src)),
GET_MODE (SUBREG_REG (p->exp)))))
@@ -5177,7 +5177,7 @@ cse_insn (rtx_insn *insn)
/* It is okay, though, if the rtx we're trying to match
will ignore any of the bits we can't predict. */
&& ! (src != 0
- && GET_CODE (src) == SUBREG
+ && SUBREG_P (src)
&& GET_MODE (src) == GET_MODE (elt->exp)
&& partial_subreg_p (GET_MODE (SUBREG_REG (src)),
GET_MODE (SUBREG_REG (elt->exp)))))
@@ -5501,7 +5501,7 @@ cse_insn (rtx_insn *insn)
&& REG_P (dest)
&& src_const
&& !REG_P (src_const)
- && !(GET_CODE (src_const) == SUBREG
+ && !(SUBREG_P (src_const)
&& REG_P (SUBREG_REG (src_const)))
&& !(GET_CODE (src_const) == CONST
&& GET_CODE (XEXP (src_const, 0)) == MINUS
@@ -5522,7 +5522,7 @@ cse_insn (rtx_insn *insn)
do_not_record = 0;
/* Look within any ZERO_EXTRACT to the MEM or REG within it. */
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -5853,7 +5853,7 @@ cse_insn (rtx_insn *insn)
previous quantity's chain.
Needed for memory if this is a nonvarying address, unless
we have just done an invalidate_memory that covers even those. */
- if (REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || SUBREG_P (dest))
invalidate (dest, VOIDmode);
else if (MEM_P (dest))
invalidate (dest, VOIDmode);
@@ -5975,7 +5975,7 @@ cse_insn (rtx_insn *insn)
if (GET_CODE (dest) == STRICT_LOW_PART)
dest = SUBREG_REG (XEXP (dest, 0));
- if (REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || SUBREG_P (dest))
/* Registers must also be inserted into chains for quantities. */
if (insert_regs (dest, sets[i].src_elt, 1))
{
@@ -6019,7 +6019,7 @@ cse_insn (rtx_insn *insn)
Note the loop below will find SUBREG_REG (DEST) since we have
already entered SRC and DEST of the SET in the table. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& (known_equal_after_align_down
(GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) - 1,
GET_MODE_SIZE (GET_MODE (dest)) - 1,
@@ -6147,7 +6147,7 @@ invalidate_from_clobbers (rtx_insn *insn)
rtx ref = XEXP (x, 0);
if (ref)
{
- if (REG_P (ref) || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || SUBREG_P (ref)
|| MEM_P (ref))
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
@@ -6170,7 +6170,7 @@ invalidate_from_clobbers (rtx_insn *insn)
if (GET_CODE (y) == CLOBBER)
{
rtx ref = XEXP (y, 0);
- if (REG_P (ref) || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || SUBREG_P (ref)
|| MEM_P (ref))
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
@@ -6231,7 +6231,7 @@ invalidate_from_sets_and_clobbers (rtx_insn *insn)
rtx clobbered = XEXP (y, 0);
if (REG_P (clobbered)
- || GET_CODE (clobbered) == SUBREG)
+ || SUBREG_P (clobbered))
invalidate (clobbered, VOIDmode);
else if (GET_CODE (clobbered) == STRICT_LOW_PART
|| GET_CODE (clobbered) == ZERO_EXTRACT)
diff --git a/gcc/cselib.c b/gcc/cselib.c
index 7b0545e779c..3575141d601 100644
--- a/gcc/cselib.c
+++ b/gcc/cselib.c
@@ -1692,7 +1692,7 @@ cselib_expand_value_rtx_1 (rtx orig, struct expand_value_data *evd,
GET_MODE (SUBREG_REG (orig)),
SUBREG_BYTE (orig));
if (scopy == NULL
- || (GET_CODE (scopy) == SUBREG
+ || (SUBREG_P (scopy)
&& !REG_P (SUBREG_REG (scopy))
&& !MEM_P (SUBREG_REG (scopy))))
return NULL;
@@ -2376,7 +2376,7 @@ cselib_invalidate_mem (rtx mem_rtx)
void
cselib_invalidate_rtx (rtx dest, const_rtx setter)
{
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/dbxout.c b/gcc/dbxout.c
index 81577dfe5cd..1d487a5475e 100644
--- a/gcc/dbxout.c
+++ b/gcc/dbxout.c
@@ -3000,11 +3000,11 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
If the decl was from an inline function, then its rtl
is not identically the rtl that was used in this
particular compilation. */
- if (GET_CODE (home) == SUBREG)
+ if (SUBREG_P (home))
{
rtx value = home;
- while (GET_CODE (value) == SUBREG)
+ while (SUBREG_P (value))
value = SUBREG_REG (value);
if (REG_P (value))
{
diff --git a/gcc/df-core.c b/gcc/df-core.c
index be19aba0f1e..1eae8dba891 100644
--- a/gcc/df-core.c
+++ b/gcc/df-core.c
@@ -1955,7 +1955,7 @@ df_find_def (rtx_insn *insn, rtx reg)
{
df_ref def;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -1984,7 +1984,7 @@ df_find_use (rtx_insn *insn, rtx reg)
{
df_ref use;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
diff --git a/gcc/df-problems.c b/gcc/df-problems.c
index d32c688510c..bc3f38a94bd 100644
--- a/gcc/df-problems.c
+++ b/gcc/df-problems.c
@@ -2811,7 +2811,7 @@ df_word_lr_mark_ref (df_ref ref, bool is_set, regset live)
int which_subword = -1;
bool changed = false;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (orig_reg);
regno = REGNO (reg);
reg_mode = GET_MODE (reg);
@@ -2819,7 +2819,7 @@ df_word_lr_mark_ref (df_ref ref, bool is_set, regset live)
|| maybe_ne (GET_MODE_SIZE (reg_mode), 2 * UNITS_PER_WORD))
return true;
- if (GET_CODE (orig_reg) == SUBREG
+ if (SUBREG_P (orig_reg)
&& read_modify_subreg_p (orig_reg))
{
gcc_assert (DF_REF_FLAGS_IS_SET (ref, DF_REF_PARTIAL));
@@ -4002,7 +4002,7 @@ find_memory_stores (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
int *pflags = (int *)data;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = XEXP (x, 0);
/* Treat stores to SP as stores to memory, this will prevent problems
when there are references to the stack frame. */
diff --git a/gcc/df-scan.c b/gcc/df-scan.c
index 03294a8a2c3..57d6efd709f 100644
--- a/gcc/df-scan.c
+++ b/gcc/df-scan.c
@@ -2474,7 +2474,7 @@ df_ref_create_structure (enum df_ref_class cl,
int ref_flags)
{
df_ref this_ref = NULL;
- unsigned int regno = REGNO (GET_CODE (reg) == SUBREG ? SUBREG_REG (reg) : reg);
+ unsigned int regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
struct df_scan_problem_data *problem_data
= (struct df_scan_problem_data *) df_scan->problem_data;
@@ -2561,9 +2561,9 @@ df_ref_record (enum df_ref_class cl,
{
unsigned int regno;
- gcc_checking_assert (REG_P (reg) || GET_CODE (reg) == SUBREG);
+ gcc_checking_assert (REG_P (reg) || SUBREG_P (reg));
- regno = REGNO (GET_CODE (reg) == SUBREG ? SUBREG_REG (reg) : reg);
+ regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
if (regno < FIRST_PSEUDO_REGISTER)
{
struct df_mw_hardreg *hardreg = NULL;
@@ -2573,7 +2573,7 @@ df_ref_record (enum df_ref_class cl,
unsigned int endregno;
df_ref ref;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
regno += subreg_regno_offset (regno, GET_MODE (SUBREG_REG (reg)),
SUBREG_BYTE (reg), GET_MODE (reg));
@@ -2590,7 +2590,7 @@ df_ref_record (enum df_ref_class cl,
{
/* Sets to a subreg of a multiword register are partial.
Sets to a non-subreg of a multiword register are not. */
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
ref_flags |= DF_REF_PARTIAL;
ref_flags |= DF_REF_MW_HARDREG;
@@ -2673,7 +2673,7 @@ df_def_record_1 (class df_collection_rec *collection_rec,
df_ref_record (DF_REF_BASE, collection_rec,
dst, NULL, bb, insn_info, DF_REF_REG_USE, flags);
}
- else if (GET_CODE (dst) == SUBREG && REG_P (SUBREG_REG (dst)))
+ else if (SUBREG_P (dst) && REG_P (SUBREG_REG (dst)))
{
if (read_modify_subreg_p (dst))
flags |= DF_REF_READ_WRITE | DF_REF_PARTIAL;
@@ -2753,7 +2753,7 @@ df_find_hard_reg_defs_1 (rtx dst, HARD_REG_SET *defs)
/* At this point if we do not have a reg or a subreg, just return. */
if (REG_P (dst) && HARD_REGISTER_P (dst))
SET_HARD_REG_BIT (*defs, REGNO (dst));
- else if (GET_CODE (dst) == SUBREG
+ else if (SUBREG_P (dst)
&& REG_P (SUBREG_REG (dst)) && HARD_REGISTER_P (dst))
SET_HARD_REG_BIT (*defs, REGNO (SUBREG_REG (dst)));
}
@@ -2919,7 +2919,7 @@ df_uses_record (class df_collection_rec *collection_rec,
SUBREG. */
dst = XEXP (dst, 0);
df_uses_record (collection_rec,
- (GET_CODE (dst) == SUBREG) ? &SUBREG_REG (dst) : temp,
+ (SUBREG_P (dst)) ? &SUBREG_REG (dst) : temp,
DF_REF_REG_USE, bb, insn_info,
DF_REF_READ_WRITE | DF_REF_STRICT_LOW_PART);
}
diff --git a/gcc/df.h b/gcc/df.h
index 2e3b825065e..039fe9e9b22 100644
--- a/gcc/df.h
+++ b/gcc/df.h
@@ -647,10 +647,10 @@ public:
/* Macros to access the elements within the ref structure. */
-#define DF_REF_REAL_REG(REF) (GET_CODE ((REF)->base.reg) == SUBREG \
+#define DF_REF_REAL_REG(REF) (SUBREG_P ((REF)->base.reg) \
? SUBREG_REG ((REF)->base.reg) : ((REF)->base.reg))
#define DF_REF_REGNO(REF) ((REF)->base.regno)
-#define DF_REF_REAL_LOC(REF) (GET_CODE (*((REF)->regular_ref.loc)) == SUBREG \
+#define DF_REF_REAL_LOC(REF) (SUBREG_P (*((REF)->regular_ref.loc)) \
? &SUBREG_REG (*((REF)->regular_ref.loc)) : ((REF)->regular_ref.loc))
#define DF_REF_REG(REF) ((REF)->base.reg)
#define DF_REF_LOC(REF) (DF_REF_CLASS (REF) == DF_REF_REGULAR ? \
diff --git a/gcc/dojump.c b/gcc/dojump.c
index bac37a357a9..040d2c260fb 100644
--- a/gcc/dojump.c
+++ b/gcc/dojump.c
@@ -610,7 +610,7 @@ do_jump (tree exp, rtx_code_label *if_false_label,
temp = expand_normal (exp);
do_pending_stack_adjust ();
/* The RTL optimizers prefer comparisons against pseudos. */
- if (GET_CODE (temp) == SUBREG)
+ if (SUBREG_P (temp))
{
/* Compare promoted variables in their promoted mode. */
if (SUBREG_PROMOTED_VAR_P (temp)
diff --git a/gcc/dse.c b/gcc/dse.c
index 40ef3fb74e3..e76d67b5748 100644
--- a/gcc/dse.c
+++ b/gcc/dse.c
@@ -1464,7 +1464,7 @@ record_store (rtx body, bb_info_t bb_info)
/* No place to keep the value after ra. */
&& !reload_completed
&& (REG_P (SET_SRC (body))
- || GET_CODE (SET_SRC (body)) == SUBREG
+ || SUBREG_P (SET_SRC (body))
|| CONSTANT_P (SET_SRC (body)))
&& !MEM_VOLATILE_P (mem)
/* Sometimes the store and reload is used for truncation and
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index 7417551b120..d1fb7bf494d 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -4222,7 +4222,7 @@ static inline int
is_pseudo_reg (const_rtx rtl)
{
return ((REG_P (rtl) && REGNO (rtl) >= FIRST_PSEUDO_REGISTER)
- || (GET_CODE (rtl) == SUBREG
+ || (SUBREG_P (rtl)
&& REGNO (SUBREG_REG (rtl)) >= FIRST_PSEUDO_REGISTER));
}
@@ -17133,7 +17133,7 @@ dw_sra_loc_expr (tree decl, rtx loc)
|| GET_CODE (varloc) == SIGN_EXTEND
|| GET_CODE (varloc) == ZERO_EXTEND)
varloc = XEXP (varloc, 0);
- else if (GET_CODE (varloc) == SUBREG)
+ else if (SUBREG_P (varloc))
varloc = SUBREG_REG (varloc);
else
break;
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index 7a811548149..13cfd0b00ea 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -1294,7 +1294,7 @@ set_reg_attrs_from_value (rtx reg, rtx x)
while (GET_CODE (x) == SIGN_EXTEND
|| GET_CODE (x) == ZERO_EXTEND
|| GET_CODE (x) == TRUNCATE
- || (GET_CODE (x) == SUBREG && subreg_lowpart_p (x)))
+ || (SUBREG_P (x) && subreg_lowpart_p (x)))
{
#if defined(POINTERS_EXTEND_UNSIGNED)
if (((GET_CODE (x) == SIGN_EXTEND && POINTERS_EXTEND_UNSIGNED)
@@ -1377,7 +1377,7 @@ set_reg_attrs_for_decl_rtl (tree t, rtx x)
if (!t)
return;
tree tdecl = t;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
gcc_assert (subreg_lowpart_p (x));
x = SUBREG_REG (x);
@@ -1595,7 +1595,7 @@ gen_lowpart_common (machine_mode mode, rtx x)
else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (int_innermode))
return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0));
}
- else if (GET_CODE (x) == SUBREG || REG_P (x)
+ else if (SUBREG_P (x) || REG_P (x)
|| GET_CODE (x) == CONCAT || CONST_VECTOR_P (x)
|| CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x)
|| CONST_POLY_INT_P (x))
@@ -1690,7 +1690,7 @@ subreg_size_highpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes)
int
subreg_lowpart_p (const_rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return 1;
else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
return 0;
@@ -3348,7 +3348,7 @@ make_safe_from (rtx x, rtx other)
if ((MEM_P (other)
&& ! CONSTANT_P (x)
&& !REG_P (x)
- && GET_CODE (x) != SUBREG)
+ && !SUBREG_P (x))
|| (REG_P (other)
&& (REGNO (other) < FIRST_PSEUDO_REGISTER
|| reg_mentioned_p (other, x))))
@@ -5416,7 +5416,7 @@ set_for_reg_notes (rtx insn)
reg = XEXP (reg, 0);
/* Check that we have a register. */
- if (!(REG_P (reg) || GET_CODE (reg) == SUBREG))
+ if (!(REG_P (reg) || SUBREG_P (reg)))
return NULL_RTX;
return pat;
diff --git a/gcc/expmed.c b/gcc/expmed.c
index c582f3a1e62..25d19a05794 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -622,7 +622,7 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
/* If xop0 is a register, we need it in OP_MODE
to make it acceptable to the format of insv. */
- if (GET_CODE (xop0) == SUBREG)
+ if (SUBREG_P (xop0))
/* We can't just change the mode, because this might clobber op0,
and we will need the original value of op0 if insv fails. */
xop0 = gen_rtx_SUBREG (op_mode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
@@ -635,7 +635,7 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
truncate the result to the original destination. Note that we can't
just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
X) 0)) is (reg:N X). */
- if (GET_CODE (xop0) == SUBREG
+ if (SUBREG_P (xop0)
&& REG_P (SUBREG_REG (xop0))
&& !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0)),
op_mode))
@@ -735,7 +735,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
{
rtx op0 = str_rtx;
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
{
bitnum += subreg_memory_offset (op0) * BITS_PER_UNIT;
op0 = SUBREG_REG (op0);
@@ -875,7 +875,7 @@ store_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
rtx arg0 = op0;
unsigned HOST_WIDE_INT subreg_off;
- if (GET_CODE (arg0) == SUBREG)
+ if (SUBREG_P (arg0))
{
/* Else we've got some float mode source being extracted into
a different float mode destination -- this combination of
@@ -1330,7 +1330,7 @@ store_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (REG_P (op0) || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || SUBREG_P (op0))
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
@@ -1375,7 +1375,7 @@ store_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
&& unit > BITS_PER_UNIT
&& maybe_gt (bitpos + bitsdone - thispos + unit, bitregion_end + 1)
&& !REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
{
unit = unit / 2;
continue;
@@ -1520,7 +1520,7 @@ extract_bit_field_using_extv (const extraction_insn *extv, rtx op0,
/* If op0 is a register, we need it in EXT_MODE to make it
acceptable to the format of ext(z)v. */
- if (GET_CODE (op0) == SUBREG && op0_mode.require () != ext_mode)
+ if (SUBREG_P (op0) && op0_mode.require () != ext_mode)
return NULL_RTX;
if (REG_P (op0) && op0_mode.require () != ext_mode)
op0 = gen_lowpart_SUBREG (ext_mode, op0);
@@ -1604,7 +1604,7 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
if (tmode == VOIDmode)
tmode = mode;
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
{
bitnum += SUBREG_BYTE (op0) * BITS_PER_UNIT;
op0 = SUBREG_REG (op0);
@@ -1764,7 +1764,7 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
/* If we got a SUBREG, force it into a register since we
aren't going to be able to do another SUBREG on it. */
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = force_reg (imode, op0);
}
else
@@ -2250,7 +2250,7 @@ extract_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (REG_P (op0) || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || SUBREG_P (op0))
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
@@ -2477,7 +2477,7 @@ expand_shift_1 (enum tree_code code, machine_mode mode, rtx shifted,
op1 = gen_int_shift_amount (mode,
(unsigned HOST_WIDE_INT) INTVAL (op1)
% GET_MODE_BITSIZE (scalar_mode));
- else if (GET_CODE (op1) == SUBREG
+ else if (SUBREG_P (op1)
&& subreg_lowpart_p (op1)
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1)))
&& SCALAR_INT_MODE_P (GET_MODE (op1)))
@@ -3349,7 +3349,7 @@ expand_mult_const (machine_mode mode, rtx op0, HOST_WIDE_INT val,
we've set the inner register and must properly indicate that. */
tem = op0, nmode = mode;
accum_inner = accum;
- if (GET_CODE (accum) == SUBREG)
+ if (SUBREG_P (accum))
{
accum_inner = SUBREG_REG (accum);
nmode = GET_MODE (accum_inner);
diff --git a/gcc/expr.c b/gcc/expr.c
index d020627203b..cb933203a2c 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -227,7 +227,7 @@ convert_move (rtx to, rtx from, int unsignedp)
TO here. */
scalar_int_mode to_int_mode;
- if (GET_CODE (from) == SUBREG
+ if (SUBREG_P (from)
&& SUBREG_PROMOTED_VAR_P (from)
&& is_a <scalar_int_mode> (to_mode, &to_int_mode)
&& (GET_MODE_PRECISION (subreg_promoted_mode (from))
@@ -238,7 +238,7 @@ convert_move (rtx to, rtx from, int unsignedp)
from_mode = to_int_mode;
}
- gcc_assert (GET_CODE (to) != SUBREG || !SUBREG_PROMOTED_VAR_P (to));
+ gcc_assert (!SUBREG_P (to) || !SUBREG_PROMOTED_VAR_P (to));
if (to_mode == from_mode
|| (from_mode == VOIDmode && CONSTANT_P (from)))
@@ -437,7 +437,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
so that we always generate the same set of insns for
better cse'ing; if an intermediate assignment occurred,
we won't be doing the operation directly on the SUBREG. */
- if (optimize > 0 && GET_CODE (from) == SUBREG)
+ if (optimize > 0 && SUBREG_P (from))
from = force_reg (from_mode, from);
emit_unop_insn (code, to, from, equiv_code);
return;
@@ -519,7 +519,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
&& ! mode_dependent_address_p (XEXP (from, 0),
MEM_ADDR_SPACE (from)))
|| REG_P (from)
- || GET_CODE (from) == SUBREG))
+ || SUBREG_P (from)))
from = force_reg (from_mode, from);
convert_move (to, gen_lowpart (word_mode, from), 0);
return;
@@ -538,7 +538,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
&& ! mode_dependent_address_p (XEXP (from, 0),
MEM_ADDR_SPACE (from)))
|| REG_P (from)
- || GET_CODE (from) == SUBREG))
+ || SUBREG_P (from)))
from = force_reg (from_mode, from);
if (REG_P (from) && REGNO (from) < FIRST_PSEUDO_REGISTER
&& !targetm.hard_regno_mode_ok (REGNO (from), to_mode))
@@ -656,7 +656,7 @@ convert_modes (machine_mode mode, machine_mode oldmode, rtx x, int unsignedp)
/* If FROM is a SUBREG that indicates that we have already done at least
the required extension, strip it. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_PROMOTED_VAR_P (x)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& (GET_MODE_PRECISION (subreg_promoted_mode (x))
@@ -3587,7 +3587,7 @@ emit_move_ccmode (machine_mode mode, rtx x, rtx y)
static bool
undefined_operand_subword_p (const_rtx op, int i)
{
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
return false;
machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
poly_int64 offset = i * UNITS_PER_WORD + subreg_memory_offset (op);
@@ -3656,7 +3656,7 @@ emit_move_multi_word (machine_mode mode, rtx x, rtx y)
gcc_assert (xpart && ypart);
- need_clobber |= (GET_CODE (xpart) == SUBREG);
+ need_clobber |= (SUBREG_P (xpart));
last_insn = emit_move_insn (xpart, ypart);
}
@@ -4759,7 +4759,7 @@ optimize_bitfield_assignment_op (poly_uint64 pbitsize,
offset1 = (offset1 - bitpos) / BITS_PER_UNIT;
str_rtx = adjust_address (str_rtx, str_mode, offset1);
}
- else if (!REG_P (str_rtx) && GET_CODE (str_rtx) != SUBREG)
+ else if (!REG_P (str_rtx) && !SUBREG_P (str_rtx))
return false;
/* If the bit field covers the whole REG/MEM, store_field
@@ -5554,7 +5554,7 @@ store_expr (tree exp, rtx target, int call_param_p,
return NULL_RTX;
}
- else if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ else if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
/* If this is a scalar in a register that is stored in a wider mode
than the declared mode, compute the result into its declared mode
and then convert to the wider mode. Our value is the computed
@@ -6953,7 +6953,7 @@ store_field (rtx target, poly_int64 bitsize, poly_int64 bitpos,
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
|| REG_P (target)
- || GET_CODE (target) == SUBREG
+ || SUBREG_P (target)
/* If the field isn't aligned enough to store as an ordinary memref,
store it as a bit field. */
|| (mode != BLKmode
@@ -7605,7 +7605,7 @@ safe_from_p (const_rtx x, tree exp, int top_p)
/* If this is a subreg of a hard register, declare it unsafe, otherwise,
find the underlying pseudo. */
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
x = SUBREG_REG (x);
if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
@@ -7749,7 +7749,7 @@ safe_from_p (const_rtx x, tree exp, int top_p)
with it. */
if (exp_rtl)
{
- if (GET_CODE (exp_rtl) == SUBREG)
+ if (SUBREG_P (exp_rtl))
{
exp_rtl = SUBREG_REG (exp_rtl);
if (REG_P (exp_rtl)
@@ -8518,7 +8518,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
a promoted SUBREG, clear that indication since we now
have to do the proper extension. */
if (TYPE_UNSIGNED (TREE_TYPE (treeop0)) != unsignedp
- && GET_CODE (op0) == SUBREG)
+ && SUBREG_P (op0))
SUBREG_PROMOTED_VAR_P (op0) = 0;
return REDUCE_BIT_FIELD (op0);
@@ -10678,7 +10678,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
for (int i = 0; i < 2; i++)
{
rtx op = read_complex_part (op0, i != 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = force_reg (GET_MODE (op), op);
rtx temp = gen_lowpart_common (GET_MODE_INNER (mode1),
op);
@@ -10803,7 +10803,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
(which we know to be the width of a basic mode), then
storing into memory, and changing the mode to BLKmode. */
if (mode1 == VOIDmode
- || REG_P (op0) || GET_CODE (op0) == SUBREG
+ || REG_P (op0) || SUBREG_P (op0)
|| (mode1 != BLKmode && ! direct_load[(int) mode1]
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT
@@ -11114,7 +11114,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
GET_MODE_PRECISION (GET_MODE (op0)))
&& !COMPLEX_MODE_P (GET_MODE (op0)))
{
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = force_reg (GET_MODE (op0), op0);
temp = gen_lowpart_common (mode, op0);
if (temp)
@@ -12271,7 +12271,7 @@ do_tablejump (rtx index, machine_mode mode, rtx range, rtx table_label,
sign-extended subreg, and RANGE does not have the sign bit set, then
we have a value that is valid for both sign and zero extension. In
this case, we get better code if we sign extend. */
- if (GET_CODE (index) == SUBREG
+ if (SUBREG_P (index)
&& SUBREG_PROMOTED_VAR_P (index)
&& SUBREG_PROMOTED_SIGNED_P (index)
&& ((width = GET_MODE_PRECISION (as_a <scalar_int_mode> (mode)))
diff --git a/gcc/final.c b/gcc/final.c
index fefc4874b24..7e5a574a5bb 100644
--- a/gcc/final.c
+++ b/gcc/final.c
@@ -2798,17 +2798,17 @@ final_scan_insn_1 (rtx_insn *insn, FILE *file, int optimize_p ATTRIBUTE_UNUSED,
&& insn != last_ignored_compare)
{
rtx src1, src2;
- if (GET_CODE (SET_SRC (set)) == SUBREG)
+ if (SUBREG_P (SET_SRC (set)))
SET_SRC (set) = alter_subreg (&SET_SRC (set), true);
src1 = SET_SRC (set);
src2 = NULL_RTX;
if (GET_CODE (SET_SRC (set)) == COMPARE)
{
- if (GET_CODE (XEXP (SET_SRC (set), 0)) == SUBREG)
+ if (SUBREG_P (XEXP (SET_SRC (set), 0)))
XEXP (SET_SRC (set), 0)
= alter_subreg (&XEXP (SET_SRC (set), 0), true);
- if (GET_CODE (XEXP (SET_SRC (set), 1)) == SUBREG)
+ if (SUBREG_P (XEXP (SET_SRC (set), 1)))
XEXP (SET_SRC (set), 1)
= alter_subreg (&XEXP (SET_SRC (set), 1), true);
if (XEXP (SET_SRC (set), 1)
@@ -3318,7 +3318,7 @@ cleanup_subreg_operands (rtx_insn *insn)
already if we are inside a match_operator expression that
matches the else clause. Instead we test the underlying
expression directly. */
- if (GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
+ if (SUBREG_P (*recog_data.operand_loc[i]))
{
recog_data.operand[i] = alter_subreg (recog_data.operand_loc[i], true);
changed = true;
@@ -3331,7 +3331,7 @@ cleanup_subreg_operands (rtx_insn *insn)
for (i = 0; i < recog_data.n_dups; i++)
{
- if (GET_CODE (*recog_data.dup_loc[i]) == SUBREG)
+ if (SUBREG_P (*recog_data.dup_loc[i]))
{
*recog_data.dup_loc[i] = alter_subreg (recog_data.dup_loc[i], true);
changed = true;
@@ -4042,7 +4042,7 @@ mark_symbol_refs_as_used (rtx x)
void
output_operand (rtx x, int code ATTRIBUTE_UNUSED)
{
- if (x && GET_CODE (x) == SUBREG)
+ if (x && SUBREG_P (x))
x = alter_subreg (&x, true);
/* X must not be a pseudo reg. */
diff --git a/gcc/function.c b/gcc/function.c
index 8274975ce33..bde93aa00e7 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -3209,7 +3209,7 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm,
/* If op1 is a hard register that is likely spilled, first
force it into a pseudo, otherwise combiner might extend
its lifetime too much. */
- if (GET_CODE (t) == SUBREG)
+ if (SUBREG_P (t))
t = SUBREG_REG (t);
if (REG_P (t)
&& HARD_REGISTER_P (t)
diff --git a/gcc/fwprop.c b/gcc/fwprop.c
index 137864cb61b..4d5b72e70e1 100644
--- a/gcc/fwprop.c
+++ b/gcc/fwprop.c
@@ -738,7 +738,7 @@ propagate_rtx (rtx x, machine_mode mode, rtx old_rtx, rtx new_rtx,
flags = 0;
if (REG_P (new_rtx)
|| CONSTANT_P (new_rtx)
- || (GET_CODE (new_rtx) == SUBREG
+ || (SUBREG_P (new_rtx)
&& REG_P (SUBREG_REG (new_rtx))
&& !paradoxical_subreg_p (new_rtx)))
flags |= PR_CAN_APPEAR;
@@ -1165,7 +1165,7 @@ forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set)
/* Only consider subregs... */
machine_mode use_mode = GET_MODE (use_reg);
- if (GET_CODE (use_reg) != SUBREG
+ if (!SUBREG_P (use_reg)
|| !REG_P (SET_DEST (def_set)))
return false;
@@ -1178,7 +1178,7 @@ forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set)
these SUBREGs just say how to treat the register. */
use_insn = DF_REF_INSN (use);
src = SET_SRC (def_set);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& REG_P (SUBREG_REG (src))
&& REGNO (SUBREG_REG (src)) >= FIRST_PSEUDO_REGISTER
&& GET_MODE (SUBREG_REG (src)) == use_mode
@@ -1327,17 +1327,17 @@ forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set)
/* If def and use are subreg, check if they match. */
reg = DF_REF_REG (use);
- if (GET_CODE (reg) == SUBREG && GET_CODE (SET_DEST (def_set)) == SUBREG)
+ if (SUBREG_P (reg) && SUBREG_P (SET_DEST (def_set)))
{
if (maybe_ne (SUBREG_BYTE (SET_DEST (def_set)), SUBREG_BYTE (reg)))
return false;
}
/* Check if the def had a subreg, but the use has the whole reg. */
- else if (REG_P (reg) && GET_CODE (SET_DEST (def_set)) == SUBREG)
+ else if (REG_P (reg) && SUBREG_P (SET_DEST (def_set)))
return false;
/* Check if the use has a subreg, but the def had the whole reg. Unlike the
previous case, the optimization is possible and often useful indeed. */
- else if (GET_CODE (reg) == SUBREG && REG_P (SET_DEST (def_set)))
+ else if (SUBREG_P (reg) && REG_P (SET_DEST (def_set)))
reg = SUBREG_REG (reg);
/* Make sure that we can treat REG as having the same mode as the
@@ -1406,7 +1406,7 @@ forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set)
set_reg_equal = (note == NULL_RTX
&& REG_P (SET_DEST (use_set))
&& !REG_P (src)
- && !(GET_CODE (src) == SUBREG
+ && !(SUBREG_P (src)
&& REG_P (SUBREG_REG (src)))
&& !reg_mentioned_p (SET_DEST (use_set),
SET_SRC (use_set))
diff --git a/gcc/gcse-common.c b/gcc/gcse-common.c
index e6e4b642b58..0e40adb44af 100644
--- a/gcc/gcse-common.c
+++ b/gcc/gcse-common.c
@@ -40,7 +40,7 @@ canon_list_insert (rtx dest, const_rtx x ATTRIBUTE_UNUSED, void *data)
int bb;
modify_pair pair;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/gcse.c b/gcc/gcse.c
index ff2771bdc04..43a0e29eaf7 100644
--- a/gcc/gcse.c
+++ b/gcc/gcse.c
@@ -984,7 +984,7 @@ mems_conflict_for_gcse_p (rtx dest, const_rtx setter ATTRIBUTE_UNUSED,
{
struct mem_conflict_info *mci = (struct mem_conflict_info *) data;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -1478,7 +1478,7 @@ record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
{
rtx_insn *last_set_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (dest))
@@ -3381,7 +3381,7 @@ get_pressure_class_and_nregs (rtx_insn *insn, int *nregs)
const_rtx set = single_set_gcse (insn);
reg = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (MEM_P (reg))
{
diff --git a/gcc/genpreds.c b/gcc/genpreds.c
index 82ed58f4960..1d9baea9f44 100644
--- a/gcc/genpreds.c
+++ b/gcc/genpreds.c
@@ -103,7 +103,7 @@ process_define_predicate (md_rtx_info *info)
(define_predicate "basereg_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return REG_POINTER (op);
})
@@ -112,7 +112,7 @@ process_define_predicate (md_rtx_info *info)
static inline int basereg_operand_1(rtx op, machine_mode mode)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return REG_POINTER (op);
}
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index e0c9522057a..b93b692cb43 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -905,7 +905,7 @@ noce_emit_move_insn (rtx x, rtx y)
start_sequence ();
/* Check that the SET_SRC is reasonable before calling emit_move_insn,
otherwise construct a suitable SET pattern ourselves. */
- insn = (OBJECT_P (y) || CONSTANT_P (y) || GET_CODE (y) == SUBREG)
+ insn = (OBJECT_P (y) || CONSTANT_P (y) || SUBREG_P (y))
? emit_move_insn (x, y)
: emit_insn (gen_rtx_SET (x, y));
seq = get_insns ();
@@ -1720,7 +1720,7 @@ noce_emit_cmove (struct noce_if_info *if_info, rtx x, enum rtx_code code,
if (reload_completed)
return NULL_RTX;
- if (GET_CODE (vtrue) == SUBREG && GET_CODE (vfalse) == SUBREG)
+ if (SUBREG_P (vtrue) && SUBREG_P (vfalse))
{
rtx reg_vtrue = SUBREG_REG (vtrue);
rtx reg_vfalse = SUBREG_REG (vfalse);
@@ -3335,7 +3335,7 @@ bb_ok_for_noce_convert_multiple_sets (basic_block test_bb)
return false;
if (!(REG_P (src)
- || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
+ || (SUBREG_P (src) && REG_P (SUBREG_REG (src))
&& subreg_lowpart_p (src))))
return false;
@@ -3710,7 +3710,7 @@ check_cond_move_block (basic_block bb,
modified earlier in the block. */
if ((REG_P (src)
&& vals->get (src))
- || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
+ || (SUBREG_P (src) && REG_P (SUBREG_REG (src))
&& vals->get (SUBREG_REG (src))))
return FALSE;
diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c
index 10673769958..58fcc5de017 100644
--- a/gcc/internal-fn.c
+++ b/gcc/internal-fn.c
@@ -658,7 +658,7 @@ expand_arith_overflow_result_store (tree lhs, rtx target,
static void
expand_ubsan_result_store (rtx target, rtx res)
{
- if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
/* If this is a scalar in a register that is stored in a wider mode
than the declared mode, compute the result into its declared mode
and then convert to the wider mode. Our value is the computed
@@ -2898,7 +2898,7 @@ expand_direct_optab_fn (internal_fn fn, gcall *stmt, direct_optab optab,
guarantee that the instruction will leave the upper bits of the
register in the state required by SUBREG_PROMOTED_SIGN. */
rtx dest = lhs_rtx;
- if (dest && GET_CODE (dest) == SUBREG && SUBREG_PROMOTED_VAR_P (dest))
+ if (dest && SUBREG_P (dest) && SUBREG_PROMOTED_VAR_P (dest))
dest = NULL_RTX;
create_output_operand (&ops[0], dest, insn_data[icode].operand[0].mode);
@@ -2926,7 +2926,7 @@ expand_direct_optab_fn (internal_fn fn, gcall *stmt, direct_optab optab,
If the return value has a nonintegral type, its mode must match
the instruction result. */
- if (GET_CODE (lhs_rtx) == SUBREG && SUBREG_PROMOTED_VAR_P (lhs_rtx))
+ if (SUBREG_P (lhs_rtx) && SUBREG_PROMOTED_VAR_P (lhs_rtx))
{
/* If this is a scalar in a register that is stored in a wider
mode than the declared mode, compute the result into its
diff --git a/gcc/ira-build.c b/gcc/ira-build.c
index c7457fa4431..200ed52ad55 100644
--- a/gcc/ira-build.c
+++ b/gcc/ira-build.c
@@ -1850,7 +1850,7 @@ create_insn_allocnos (rtx x, rtx outer, bool output_p)
if ((a = ira_curr_regno_allocno_map[regno]) == NULL)
{
a = ira_create_allocno (regno, false, ira_curr_loop_tree_node);
- if (outer != NULL && GET_CODE (outer) == SUBREG)
+ if (outer != NULL && SUBREG_P (outer))
{
machine_mode wmode = GET_MODE (outer);
if (partial_subreg_p (ALLOCNO_WMODE (a), wmode))
diff --git a/gcc/ira-conflicts.c b/gcc/ira-conflicts.c
index 813a6d4103c..fc471bb8770 100644
--- a/gcc/ira-conflicts.c
+++ b/gcc/ira-conflicts.c
@@ -207,7 +207,7 @@ allocnos_conflict_for_copy_p (ira_allocno_t a1, ira_allocno_t a2)
/* Check that X is REG or SUBREG of REG. */
#define REG_SUBREG_P(x) \
- (REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))))
+ (REG_P (x) || (SUBREG_P (x) && REG_P (SUBREG_REG (x))))
/* Return X if X is a REG, otherwise it should be SUBREG of REG and
the function returns the reg in this case. *OFFSET will be set to
@@ -220,7 +220,7 @@ go_through_subreg (rtx x, int *offset)
*offset = 0;
if (REG_P (x))
return x;
- ira_assert (GET_CODE (x) == SUBREG);
+ ira_assert (SUBREG_P (x));
reg = SUBREG_REG (x);
ira_assert (REG_P (reg));
if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index c49f84d621f..1838a0ea538 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -1297,11 +1297,11 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& known_eq (GET_MODE_SIZE (GET_MODE (dest)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))))
dest = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& known_eq (GET_MODE_SIZE (GET_MODE (src)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
src = SUBREG_REG (src);
@@ -1404,7 +1404,7 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
{
memcpy (op_costs[i], init_cost, struct_costs_size);
- if (GET_CODE (recog_data.operand[i]) == SUBREG)
+ if (SUBREG_P (recog_data.operand[i]))
recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
if (MEM_P (recog_data.operand[i]))
@@ -1542,7 +1542,7 @@ scan_one_insn (rtx_insn *insn)
{
rtx op = recog_data.operand[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
{
diff --git a/gcc/ira-emit.c b/gcc/ira-emit.c
index 255af307b3c..846dd5d501b 100644
--- a/gcc/ira-emit.c
+++ b/gcc/ira-emit.c
@@ -941,7 +941,7 @@ emit_move_list (move_t list, int freq)
if ((set = single_set (insn)) != NULL_RTX)
{
dest = SET_DEST (set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
ira_assert (REG_P (dest));
regno = REGNO (dest);
diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c
index 2029027125a..f1fae3c1ec7 100644
--- a/gcc/ira-lives.c
+++ b/gcc/ira-lives.c
@@ -416,7 +416,7 @@ mark_ref_live (df_ref ref)
rtx reg = DF_REF_REG (ref);
rtx orig_reg = reg;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -545,11 +545,11 @@ mark_ref_dead (df_ref def)
if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
return;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
- && (GET_CODE (orig_reg) != SUBREG
+ && (!SUBREG_P (orig_reg)
|| REGNO (reg) < FIRST_PSEUDO_REGISTER
|| !read_modify_subreg_p (orig_reg)))
return;
@@ -573,7 +573,7 @@ make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
rtx orig_reg = reg;
ira_allocno_t a;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
@@ -646,7 +646,7 @@ check_and_make_def_conflict (int alt, int def, enum reg_class def_cl)
if (def_cl == NO_REGS)
return;
- if (GET_CODE (dreg) == SUBREG)
+ if (SUBREG_P (dreg))
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
@@ -766,7 +766,7 @@ mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
{
rtx dreg = DF_REF_REG (def);
- if (GET_CODE (dreg) == SUBREG)
+ if (SUBREG_P (dreg))
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
continue;
@@ -875,7 +875,7 @@ ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
{
op = recog_data.operand[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == SCRATCH
@@ -934,7 +934,7 @@ process_single_reg_class_operands (bool in_p, int freq)
operand_a = NULL;
- if (GET_CODE (operand) == SUBREG)
+ if (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if (REG_P (operand)
@@ -1337,7 +1337,7 @@ process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
{
rtx ureg = DF_REF_REG (use);
- if (GET_CODE (ureg) == SUBREG)
+ if (SUBREG_P (ureg))
ureg = SUBREG_REG (ureg);
if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
continue;
diff --git a/gcc/ira.c b/gcc/ira.c
index ac3493f202f..84bff57fc95 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -3323,7 +3323,7 @@ set_paradoxical_subreg (rtx_insn *insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
{
const_rtx subreg = *iter;
- if (GET_CODE (subreg) == SUBREG)
+ if (SUBREG_P (subreg))
{
const_rtx reg = SUBREG_REG (subreg);
if (REG_P (reg) && paradoxical_subreg_p (subreg))
@@ -4225,7 +4225,7 @@ build_insn_chain (void)
conservative and treat the definition as a partial
definition of the full register rather than a full
definition of a specific part of the register. */
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)
&& get_subreg_tracking_sizes (reg, &outer_size,
&inner_size, &start))
@@ -4321,7 +4321,7 @@ build_insn_chain (void)
|| pseudo_for_reload_consideration_p (regno))
{
HOST_WIDE_INT outer_size, inner_size, start;
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& !DF_REF_FLAGS_IS_SET (use,
DF_REF_SIGN_EXTRACT
| DF_REF_ZERO_EXTRACT)
diff --git a/gcc/jump.c b/gcc/jump.c
index ce5cee523c3..d6f4741e9f0 100644
--- a/gcc/jump.c
+++ b/gcc/jump.c
@@ -1690,7 +1690,7 @@ rtx_renumbered_equal_p (const_rtx x, const_rtx y)
return 1;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG
+ && (REG_P (y) || (SUBREG_P (y)
&& REG_P (SUBREG_REG (y)))))
{
int reg_x = -1, reg_y = -1;
@@ -1728,7 +1728,7 @@ rtx_renumbered_equal_p (const_rtx x, const_rtx y)
reg_x = reg_renumber[reg_x];
}
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
{
reg_y = REGNO (SUBREG_REG (y));
byte_y = SUBREG_BYTE (y);
@@ -1900,7 +1900,7 @@ true_regnum (const_rtx x)
return reg_renumber[REGNO (x)];
return REGNO (x);
}
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
int base = true_regnum (SUBREG_REG (x));
if (base >= 0
@@ -1924,7 +1924,7 @@ true_regnum (const_rtx x)
unsigned int
reg_or_subregno (const_rtx reg)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
return REGNO (reg);
diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
index 644ecfc6fbb..a69eec6cda5 100644
--- a/gcc/loop-invariant.c
+++ b/gcc/loop-invariant.c
@@ -1269,7 +1269,7 @@ get_pressure_class_and_nregs (rtx_insn *insn, int *nregs)
/* Considered invariant insns have only one set. */
gcc_assert (set != NULL_RTX);
reg = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (MEM_P (reg))
{
@@ -1793,7 +1793,7 @@ move_invariant_reg (class loop *loop, unsigned invno)
need to create a temporary register. */
set = single_set (inv->insn);
reg = dest = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg))
regno = REGNO (reg);
@@ -2060,7 +2060,7 @@ static void
mark_reg_store (rtx reg, const_rtx setter ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
diff --git a/gcc/loop-iv.c b/gcc/loop-iv.c
index 2274cc3075b..5c39106170b 100644
--- a/gcc/loop-iv.c
+++ b/gcc/loop-iv.c
@@ -219,7 +219,7 @@ simple_reg_p (rtx reg)
{
unsigned r;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
if (!subreg_lowpart_p (reg))
return false;
@@ -338,7 +338,7 @@ iv_get_reaching_def (rtx_insn *insn, rtx reg, df_ref *def)
*def = NULL;
if (!simple_reg_p (reg))
return GRD_INVALID;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -680,7 +680,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
(set x':DI (plus:DI y:DI 1))
(set x:SI (subreg:SI (x':DI)). */
- if (GET_CODE (op0) != SUBREG)
+ if (!SUBREG_P (op0))
return false;
if (GET_MODE (SUBREG_REG (op0)) != outer_mode)
return false;
@@ -705,7 +705,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
return false;
}
- if (GET_CODE (next) == SUBREG)
+ if (SUBREG_P (next))
{
if (!subreg_lowpart_p (next))
return false;
@@ -737,7 +737,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
outer_step))
return false;
- if (GET_CODE (next) == SUBREG)
+ if (SUBREG_P (next))
{
scalar_int_mode amode;
if (!is_a <scalar_int_mode> (GET_MODE (next), &amode)
@@ -1119,7 +1119,7 @@ iv_analyze_op (rtx_insn *insn, scalar_int_mode mode, rtx op, class rtx_iv *iv)
if (function_invariant_p (op))
res = GRD_INVARIANT;
- else if (GET_CODE (op) == SUBREG)
+ else if (SUBREG_P (op))
{
scalar_int_mode inner_mode;
if (!subreg_lowpart_p (op)
@@ -1175,7 +1175,7 @@ iv_analyze (rtx_insn *insn, scalar_int_mode mode, rtx val, class rtx_iv *iv)
following insns. */
if (simple_reg_p (val))
{
- if (GET_CODE (val) == SUBREG)
+ if (SUBREG_P (val))
reg = SUBREG_REG (val);
else
reg = val;
@@ -1321,7 +1321,7 @@ altered_reg_used (const_rtx x, bitmap alt)
static void
mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt)
{
- if (GET_CODE (expr) == SUBREG)
+ if (SUBREG_P (expr))
expr = SUBREG_REG (expr);
if (!REG_P (expr))
return;
@@ -1502,7 +1502,7 @@ implies_p (rtx a, rtx b)
op1 = XEXP (a, 1);
if (REG_P (op0)
- || (GET_CODE (op0) == SUBREG
+ || (SUBREG_P (op0)
&& REG_P (SUBREG_REG (op0))))
{
rtx r = simplify_replace_rtx (b, op0, op1);
@@ -1511,7 +1511,7 @@ implies_p (rtx a, rtx b)
}
if (REG_P (op1)
- || (GET_CODE (op1) == SUBREG
+ || (SUBREG_P (op1)
&& REG_P (SUBREG_REG (op1))))
{
rtx r = simplify_replace_rtx (b, op1, op0);
diff --git a/gcc/loop-unroll.c b/gcc/loop-unroll.c
index 63fccd23fae..b75d13492c5 100644
--- a/gcc/loop-unroll.c
+++ b/gcc/loop-unroll.c
@@ -1419,7 +1419,7 @@ analyze_insn_to_expand_var (class loop *loop, rtx_insn *insn)
return NULL;
if (!REG_P (dest)
- && !(GET_CODE (dest) == SUBREG
+ && !(SUBREG_P (dest)
&& REG_P (SUBREG_REG (dest))))
return NULL;
diff --git a/gcc/lower-subreg.c b/gcc/lower-subreg.c
index e1418e5ec51..ea09cd39cc1 100644
--- a/gcc/lower-subreg.c
+++ b/gcc/lower-subreg.c
@@ -300,7 +300,7 @@ init_lower_subreg (void)
static bool
simple_move_operand (rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (!OBJECT_P (x))
@@ -492,7 +492,7 @@ find_decomposable_subregs (rtx *loc, enum classify_move_insn *pcmi)
FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
{
rtx x = *iter;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
rtx inner = SUBREG_REG (x);
unsigned int regno, outer_size, inner_size, outer_words, inner_words;
@@ -698,7 +698,7 @@ simplify_gen_subreg_concatn (machine_mode outermode, rtx op,
If OP is a SUBREG of a CONCATN, then it must be a simple mode
change with the same size and offset 0, or it must extract a
part. We shouldn't see anything else here. */
- if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == CONCATN)
+ if (SUBREG_P (op) && GET_CODE (SUBREG_REG (op)) == CONCATN)
{
rtx op2;
@@ -757,7 +757,7 @@ resolve_reg_p (rtx x)
static bool
resolve_subreg_p (rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
return resolve_reg_p (SUBREG_REG (x));
}
@@ -933,7 +933,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
}
}
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& resolve_reg_p (SUBREG_REG (src))
&& (maybe_ne (SUBREG_BYTE (src), 0)
|| maybe_ne (orig_size, GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))))
@@ -947,7 +947,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
/* Similarly if we are copying to a SUBREG of a decomposed reg where
the SUBREG is larger than word size. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& resolve_reg_p (SUBREG_REG (dest))
&& (maybe_ne (SUBREG_BYTE (dest), 0)
|| maybe_ne (orig_size,
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index e2a0c0afe3d..65ccbf3798f 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -162,7 +162,7 @@ static int new_insn_uid_start;
static inline rtx *
strip_subreg (rtx *loc)
{
- return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
+ return loc && SUBREG_P (*loc) ? &SUBREG_REG (*loc) : loc;
}
/* Return hard regno of REGNO or if it is was not assigned to a hard
@@ -269,7 +269,7 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
&& curr_insn_set != NULL
&& ((OBJECT_P (SET_SRC (curr_insn_set))
&& ! CONSTANT_P (SET_SRC (curr_insn_set)))
- || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
+ || (SUBREG_P (SET_SRC (curr_insn_set))
&& OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
&& ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
/* When we don't know what class will be used finally for reload
@@ -601,7 +601,7 @@ get_reload_reg (enum op_type type, machine_mode mode, rtx original,
GET_MODE_SIZE (mode)))
continue;
reg = lowpart_subreg (mode, reg, GET_MODE (reg));
- if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
+ if (reg == NULL_RTX || !SUBREG_P (reg))
continue;
}
*result_reg = reg;
@@ -680,7 +680,7 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (x == y)
return true;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
+ && (REG_P (y) || (SUBREG_P (y) && REG_P (SUBREG_REG (y)))))
{
int j;
@@ -717,7 +717,7 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (code == REG && REG_P (y))
return REGNO (x) == REGNO (y);
- if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
+ if (code == REG && SUBREG_P (y) && REG_P (SUBREG_REG (y))
&& x == SUBREG_REG (y))
return true;
if (REG_P (y) && code == SUBREG && REG_P (SUBREG_REG (x))
@@ -829,7 +829,7 @@ narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
registers for several reloads of one insn. */
if (INSN_UID (curr_insn) >= new_insn_uid_start)
return;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
return;
@@ -946,7 +946,7 @@ match_reload (signed char out, signed char *ins, signed char *outs,
rtx_insn *clobber = emit_clobber (new_out_reg);
LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
LRA_SUBREG_P (new_in_reg) = 1;
- if (GET_CODE (in_rtx) == SUBREG)
+ if (SUBREG_P (in_rtx))
{
rtx subreg_reg = SUBREG_REG (in_rtx);
@@ -1125,7 +1125,7 @@ emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
if (! MEM_P (val))
{
val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
- GET_CODE (val) == SUBREG
+ SUBREG_P (val)
? SUBREG_REG (val) : val);
LRA_SUBREG_P (val) = 1;
}
@@ -1156,9 +1156,9 @@ check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
lra_assert (curr_insn_set != NULL_RTX);
dreg = dest = SET_DEST (curr_insn_set);
sreg = src = SET_SRC (curr_insn_set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dreg = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
sreg = SUBREG_REG (src);
if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
return false;
@@ -1355,7 +1355,7 @@ process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **aft
machine_mode mode;
bool subreg_p, before_p = false;
- subreg_p = GET_CODE (*loc) == SUBREG;
+ subreg_p = SUBREG_P (*loc);
if (subreg_p)
{
reg = SUBREG_REG (*loc);
@@ -1483,7 +1483,7 @@ simplify_operand_subreg (int nop, machine_mode reg_mode)
before = after = NULL;
- if (GET_CODE (operand) != SUBREG)
+ if (!SUBREG_P (operand))
return false;
mode = GET_MODE (operand);
@@ -1961,7 +1961,7 @@ process_alt_operands (int only_alternative)
operand_reg[nop] = reg = op;
biggest_mode[nop] = GET_MODE (op);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
biggest_mode[nop] = wider_subreg_mode (op);
operand_reg[nop] = reg = SUBREG_REG (op);
@@ -2600,7 +2600,7 @@ process_alt_operands (int only_alternative)
if (curr_static_id->operand[nop].strict_low
&& REG_P (op)
&& hard_regno[nop] < 0
- && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
+ && SUBREG_P (*curr_id->operand_loc[nop])
&& ira_class_hard_regs_num[this_alternative] > 0
&& (!targetm.hard_regno_mode_ok
(ira_class_hard_regs[this_alternative][0],
@@ -2904,7 +2904,7 @@ process_alt_operands (int only_alternative)
if (curr_insn_set != NULL_RTX && n_operands == 2
/* Prevent processing non-move insns. */
- && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
+ && (SUBREG_P (SET_SRC (curr_insn_set))
|| SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
&& ((! curr_alt_win[0] && ! curr_alt_win[1]
&& REG_P (no_subreg_reg_operand[0])
@@ -3338,7 +3338,7 @@ process_address_1 (int nop, bool check_only_p,
&& get_constraint_type (cn) == CT_FIXED_FORM
&& constraint_satisfied_p (op, cn)))
decompose_mem_address (&ad, op);
- else if (GET_CODE (op) == SUBREG
+ else if (SUBREG_P (op)
&& MEM_P (SUBREG_REG (op)))
decompose_mem_address (&ad, SUBREG_REG (op));
else
@@ -3886,7 +3886,7 @@ curr_insn_transform (bool check_only_p)
continue;
old = op = *curr_id->operand_loc[i];
- if (GET_CODE (old) == SUBREG)
+ if (SUBREG_P (old))
old = SUBREG_REG (old);
subst = get_equiv_with_elimination (old, curr_insn);
original_subreg_reg_mode[i] = VOIDmode;
@@ -3896,7 +3896,7 @@ curr_insn_transform (bool check_only_p)
equiv_substition_p[i] = true;
subst = copy_rtx (subst);
lra_assert (REG_P (old));
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
*curr_id->operand_loc[i] = subst;
else
{
@@ -4154,7 +4154,7 @@ curr_insn_transform (bool check_only_p)
enum reg_class new_class;
rtx reg = *curr_id->operand_loc[i];
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
@@ -4176,7 +4176,7 @@ curr_insn_transform (bool check_only_p)
rtx subreg = NULL_RTX;
machine_mode mode = curr_operand_mode[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
subreg = op;
op = SUBREG_REG (op);
@@ -4272,10 +4272,10 @@ curr_insn_transform (bool check_only_p)
&& (curr_insn_set == NULL_RTX
|| !((REG_P (SET_SRC (curr_insn_set))
|| MEM_P (SET_SRC (curr_insn_set))
- || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
+ || SUBREG_P (SET_SRC (curr_insn_set)))
&& (REG_P (SET_DEST (curr_insn_set))
|| MEM_P (SET_DEST (curr_insn_set))
- || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
+ || SUBREG_P (SET_DEST (curr_insn_set))))))
optional_p = true;
else if (goal_alt_matched[i][0] != -1
&& curr_static_id->operand[i].type == OP_OUT
@@ -4355,7 +4355,7 @@ curr_insn_transform (bool check_only_p)
loc = curr_id->operand_loc[i];
mode = curr_operand_mode[i];
- if (GET_CODE (*loc) == SUBREG)
+ if (SUBREG_P (*loc))
{
reg = SUBREG_REG (*loc);
poly_int64 byte = SUBREG_BYTE (*loc);
@@ -4485,7 +4485,7 @@ curr_insn_transform (bool check_only_p)
lra_assert (REG_P (reg));
regno = REGNO (reg);
op = *curr_id->operand_loc[i]; /* Substitution. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
@@ -4948,7 +4948,7 @@ lra_constraints (bool first_p)
/* The equivalence pseudo could be set up as SUBREG in a
case when it is a call restore insn in a mode
different from the pseudo mode. */
- if (GET_CODE (dest_reg) == SUBREG)
+ if (SUBREG_P (dest_reg))
dest_reg = SUBREG_REG (dest_reg);
if ((REG_P (dest_reg)
&& (x = get_equiv (dest_reg)) != dest_reg
@@ -6765,7 +6765,7 @@ fix_bb_live_info (bitmap live, bitmap removed_pseudos)
static int
get_regno (rtx reg)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg))
return REGNO (reg);
@@ -6950,7 +6950,7 @@ remove_inheritance_pseudos (bitmap remove_pseudos)
&& (restore_rtx
= lra_reg_info[dregno].restore_rtx) != NULL_RTX)
{
- if (GET_CODE (SET_DEST (set)) == SUBREG)
+ if (SUBREG_P (SET_DEST (set)))
SUBREG_REG (SET_DEST (set)) = restore_rtx;
else
SET_DEST (set) = restore_rtx;
diff --git a/gcc/lra-eliminations.c b/gcc/lra-eliminations.c
index 943da888848..a9d650dab7e 100644
--- a/gcc/lra-eliminations.c
+++ b/gcc/lra-eliminations.c
@@ -287,7 +287,7 @@ move_plus_up (rtx x)
rtx subreg_reg;
machine_mode x_mode, subreg_reg_mode;
- if (GET_CODE (x) != SUBREG || !subreg_lowpart_p (x))
+ if (!SUBREG_P (x) || !subreg_lowpart_p (x))
return x;
subreg_reg = SUBREG_REG (x);
x_mode = GET_MODE (x);
@@ -932,7 +932,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
+ if (SUBREG_P (reg) && subreg_lowpart_p (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -943,7 +943,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg) && (ep = get_elimination (reg)) != NULL)
@@ -964,7 +964,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
}
- if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
+ if (SUBREG_P (XEXP (plus_cst_src, 0)))
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), to_rtx);
/* If we have a nonzero offset, and the source is already a
simple REG, the following transformation would increase
diff --git a/gcc/lra.c b/gcc/lra.c
index d7593998f97..f7790f2e154 100644
--- a/gcc/lra.c
+++ b/gcc/lra.c
@@ -384,9 +384,9 @@ lra_emit_add (rtx x, rtx y, rtx z)
base = a1;
index = a2;
}
- if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG))
+ if ((base != NULL_RTX && ! (REG_P (base) || SUBREG_P (base)))
|| (index != NULL_RTX
- && ! (REG_P (index) || GET_CODE (index) == SUBREG))
+ && ! (REG_P (index) || SUBREG_P (index)))
|| (disp != NULL_RTX && ! CONSTANT_P (disp))
|| (scale != NULL_RTX && ! CONSTANT_P (scale)))
{
@@ -1459,7 +1459,7 @@ add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x,
code = GET_CODE (x);
mode = GET_MODE (x);
subreg_p = false;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
mode = wider_subreg_mode (x);
if (read_modify_subreg_p (x))
diff --git a/gcc/mode-switching.c b/gcc/mode-switching.c
index d706e02faf7..5e3bacb1e18 100644
--- a/gcc/mode-switching.c
+++ b/gcc/mode-switching.c
@@ -212,7 +212,7 @@ reg_becomes_live (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *live)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg))
@@ -360,7 +360,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
copy_reg = SET_DEST (return_copy_pat);
if (REG_P (copy_reg))
copy_start = REGNO (copy_reg);
- else if (GET_CODE (copy_reg) == SUBREG
+ else if (SUBREG_P (copy_reg)
&& REG_P (SUBREG_REG (copy_reg)))
copy_start = REGNO (SUBREG_REG (copy_reg));
else
diff --git a/gcc/modulo-sched.c b/gcc/modulo-sched.c
index c355594bb6b..4ebd514daed 100644
--- a/gcc/modulo-sched.c
+++ b/gcc/modulo-sched.c
@@ -1477,7 +1477,7 @@ sms_schedule (void)
&& !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
&& !reg_mentioned_p (count_reg, insn))
|| (INSN_P (insn) && (set = single_set (insn))
- && GET_CODE (SET_DEST (set)) == SUBREG))
+ && SUBREG_P (SET_DEST (set))))
break;
}
diff --git a/gcc/optabs.c b/gcc/optabs.c
index 06bcaab1f55..9692ded0f38 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -208,7 +208,7 @@ widen_operand (rtx op, machine_mode mode, machine_mode oldmode,
a promoted object differs from our extension. */
if (! no_extend
|| !is_a <scalar_int_mode> (mode, &int_mode)
- || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op)
+ || (SUBREG_P (op) && SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_CHECK_PROMOTED_SIGN (op, unsignedp)))
return convert_modes (mode, oldmode, op, unsignedp);
diff --git a/gcc/postreload-gcse.c b/gcc/postreload-gcse.c
index e4737670883..429a44a4762 100644
--- a/gcc/postreload-gcse.c
+++ b/gcc/postreload-gcse.c
@@ -618,7 +618,7 @@ find_mem_conflicts (rtx dest, const_rtx setter ATTRIBUTE_UNUSED,
{
rtx mem_op = (rtx) data;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -733,7 +733,7 @@ record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
{
rtx_insn *last_set_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (dest))
diff --git a/gcc/postreload.c b/gcc/postreload.c
index 728aa9b0ed5..8f2c3448eb4 100644
--- a/gcc/postreload.c
+++ b/gcc/postreload.c
@@ -1418,7 +1418,7 @@ reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
int i;
machine_mode mode = GET_MODE (dst);
- if (GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (dst))
{
regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
GET_MODE (SUBREG_REG (dst)),
@@ -1670,7 +1670,7 @@ move2add_record_mode (rtx reg)
int regno, nregs;
machine_mode mode = GET_MODE (reg);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
regno = subreg_regno (reg);
nregs = subreg_nregs (reg);
@@ -2188,7 +2188,7 @@ move2add_note_store (rtx dst, const_rtx set, void *data)
return;
}
- if (GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (dst))
regno = subreg_regno (dst);
else if (REG_P (dst))
regno = REGNO (dst);
diff --git a/gcc/read-rtl.c b/gcc/read-rtl.c
index 3b5d9997603..3dcf35b8f17 100644
--- a/gcc/read-rtl.c
+++ b/gcc/read-rtl.c
@@ -255,7 +255,7 @@ find_int (const char *name)
static void
apply_int_iterator (rtx x, unsigned int index, int value)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
SUBREG_BYTE (x) = value;
else
XINT (x, index) = value;
diff --git a/gcc/recog.c b/gcc/recog.c
index dffe8bfde75..56bd5716a87 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -1087,7 +1087,7 @@ address_operand (rtx op, machine_mode mode)
int
register_operand (rtx op, machine_mode mode)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
rtx sub = SUBREG_REG (op);
@@ -1360,7 +1360,7 @@ memory_operand (rtx op, machine_mode mode)
return 0;
inner = op;
- if (GET_CODE (inner) == SUBREG)
+ if (SUBREG_P (inner))
inner = SUBREG_REG (inner);
return (MEM_P (inner) && general_operand (op, mode));
@@ -1374,7 +1374,7 @@ indirect_operand (rtx op, machine_mode mode)
{
/* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
if (! reload_completed
- && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
+ && SUBREG_P (op) && MEM_P (SUBREG_REG (op)))
{
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
@@ -2603,7 +2603,7 @@ constrain_operands (int strict, alternative_mask alternatives)
if (UNARY_P (op))
op = XEXP (op, 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (REG_P (SUBREG_REG (op))
&& REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
diff --git a/gcc/ree.c b/gcc/ree.c
index e4de9743e4c..ddd31ab6c06 100644
--- a/gcc/ree.c
+++ b/gcc/ree.c
@@ -467,7 +467,7 @@ get_defs (rtx_insn *insn, rtx reg, vec<rtx_insn *> *dest)
FOR_EACH_INSN_USE (use, insn)
{
- if (GET_CODE (DF_REF_REG (use)) == SUBREG)
+ if (SUBREG_P (DF_REF_REG (use)))
return NULL;
if (REGNO (DF_REF_REG (use)) == REGNO (reg))
break;
diff --git a/gcc/reg-stack.c b/gcc/reg-stack.c
index c730b324cc0..45b0b35160a 100644
--- a/gcc/reg-stack.c
+++ b/gcc/reg-stack.c
@@ -492,7 +492,7 @@ check_asm_stack_operands (rtx_insn *insn)
/* Strip SUBREGs here to make the following code simpler. */
for (i = 0; i < recog_data.n_operands; i++)
- if (GET_CODE (recog_data.operand[i]) == SUBREG
+ if (SUBREG_P (recog_data.operand[i])
&& REG_P (SUBREG_REG (recog_data.operand[i])))
recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
@@ -510,7 +510,7 @@ check_asm_stack_operands (rtx_insn *insn)
rtx clobber = XVECEXP (body, 0, i);
rtx reg = XEXP (clobber, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
reg = SUBREG_REG (reg);
if (STACK_REG_P (reg))
@@ -2139,7 +2139,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
/* Strip SUBREGs here to make the following code simpler. */
for (i = 0; i < recog_data.n_operands; i++)
- if (GET_CODE (recog_data.operand[i]) == SUBREG
+ if (SUBREG_P (recog_data.operand[i])
&& REG_P (SUBREG_REG (recog_data.operand[i])))
{
recog_data.operand_loc[i] = & SUBREG_REG (recog_data.operand[i]);
@@ -2163,7 +2163,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
rtx reg = XEXP (note, 0);
rtx *loc = & XEXP (note, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
{
loc = & SUBREG_REG (reg);
reg = SUBREG_REG (reg);
@@ -2196,7 +2196,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
rtx reg = XEXP (clobber, 0);
rtx *loc = & XEXP (clobber, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
{
loc = & SUBREG_REG (reg);
reg = SUBREG_REG (reg);
diff --git a/gcc/regcprop.c b/gcc/regcprop.c
index a18c24f4797..680cf15e719 100644
--- a/gcc/regcprop.c
+++ b/gcc/regcprop.c
@@ -189,7 +189,7 @@ kill_value_regno (unsigned int regno, unsigned int nregs,
static void
kill_value (const_rtx x, struct value_data *vd)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
rtx tmp = simplify_subreg (GET_MODE (x), SUBREG_REG (x),
GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
@@ -541,13 +541,13 @@ replace_oldest_value_addr (rtx *loc, enum reg_class cl,
rtx *locB = NULL;
enum rtx_code index_code = SCRATCH;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
diff --git a/gcc/reginfo.c b/gcc/reginfo.c
index 4832affd436..22129db915a 100644
--- a/gcc/reginfo.c
+++ b/gcc/reginfo.c
@@ -1109,7 +1109,7 @@ reg_scan_mark_refs (rtx x, rtx_insn *insn)
case SET:
/* Count a set of the destination if it is a register. */
for (dest = SET_DEST (x);
- GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
+ SUBREG_P (dest) || GET_CODE (dest) == STRICT_LOW_PART
|| GET_CODE (dest) == ZERO_EXTRACT;
dest = XEXP (dest, 0))
;
diff --git a/gcc/regrename.c b/gcc/regrename.c
index 3b144f5e38b..0ce4d180880 100644
--- a/gcc/regrename.c
+++ b/gcc/regrename.c
@@ -1055,7 +1055,7 @@ note_sets_clobbers (rtx x, const_rtx set, void *data)
enum rtx_code code = *(enum rtx_code *)data;
class du_head *chain;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (!REG_P (x) || GET_CODE (set) != code)
return;
@@ -1291,13 +1291,13 @@ scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl,
rtx *locB = NULL;
enum rtx_code index_code = SCRATCH;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
diff --git a/gcc/reload.c b/gcc/reload.c
index 72cc38a0e09..e1f8329297c 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -840,7 +840,7 @@ reload_inner_reg_of_subreg (rtx x, machine_mode mode, bool output)
rtx inner;
/* Only SUBREGs are problematical. */
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
inner = SUBREG_REG (x);
@@ -1051,7 +1051,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
no choice, so we hope we do get the right register class there. */
scalar_int_mode inner_mode;
- if (in != 0 && GET_CODE (in) == SUBREG
+ if (in != 0 && SUBREG_P (in)
&& (subreg_lowpart_p (in) || strict_low)
&& targetm.can_change_mode_class (GET_MODE (SUBREG_REG (in)),
inmode, rclass)
@@ -1149,7 +1149,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
entitled to clobber it all (except in the case of a word mode subreg
or of a STRICT_LOW_PART, in that latter case the constraint should
label it input-output.) */
- if (out != 0 && GET_CODE (out) == SUBREG
+ if (out != 0 && SUBREG_P (out)
&& (subreg_lowpart_p (out) || strict_low)
&& targetm.can_change_mode_class (GET_MODE (SUBREG_REG (out)),
outmode, rclass)
@@ -1232,13 +1232,13 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
/* If IN is a SUBREG of a hard register, make a new REG. This
simplifies some of the cases below. */
- if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))
+ if (in != 0 && SUBREG_P (in) && REG_P (SUBREG_REG (in))
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
&& ! dont_remove_subreg)
in = gen_rtx_REG (GET_MODE (in), subreg_regno (in));
/* Similarly for OUT. */
- if (out != 0 && GET_CODE (out) == SUBREG
+ if (out != 0 && SUBREG_P (out)
&& REG_P (SUBREG_REG (out))
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
&& ! dont_remove_subreg)
@@ -1270,12 +1270,12 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
#ifdef LIMIT_RELOAD_CLASS
if (in_subreg_loc)
rclass = LIMIT_RELOAD_CLASS (inmode, rclass);
- else if (in != 0 && GET_CODE (in) == SUBREG)
+ else if (in != 0 && SUBREG_P (in))
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), rclass);
if (out_subreg_loc)
rclass = LIMIT_RELOAD_CLASS (outmode, rclass);
- if (out != 0 && GET_CODE (out) == SUBREG)
+ if (out != 0 && SUBREG_P (out))
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), rclass);
#endif
@@ -1351,7 +1351,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
if (subreg_in_class == NO_REGS
&& in != 0
&& (REG_P (in)
- || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
+ || (SUBREG_P (in) && REG_P (SUBREG_REG (in))))
&& reg_or_subregno (in) < FIRST_PSEUDO_REGISTER)
subreg_in_class = REGNO_REG_CLASS (reg_or_subregno (in));
/* If a memory location is needed for the copy, make one. */
@@ -1383,7 +1383,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
if (out != 0
&& (REG_P (out)
- || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
+ || (SUBREG_P (out) && REG_P (SUBREG_REG (out))))
&& reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
&& (targetm.secondary_memory_needed
(outmode, rclass, REGNO_REG_CLASS (reg_or_subregno (out)))))
@@ -1597,7 +1597,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
Is there any simple coherent way to describe the two together?
What's going on here. */
&& (in != out
- || (GET_CODE (in) == SUBREG
+ || (SUBREG_P (in)
&& (known_equal_after_align_up
(GET_MODE_SIZE (GET_MODE (in)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))),
@@ -1951,7 +1951,7 @@ find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
respectively refers to a hard register. */
/* Find the inside of any subregs. */
- while (GET_CODE (out) == SUBREG)
+ while (SUBREG_P (out))
{
if (REG_P (SUBREG_REG (out))
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER)
@@ -1961,7 +1961,7 @@ find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
GET_MODE (out));
out = SUBREG_REG (out);
}
- while (GET_CODE (in) == SUBREG)
+ while (SUBREG_P (in))
{
if (REG_P (SUBREG_REG (in))
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER)
@@ -2134,7 +2134,7 @@ hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x)
{
rtx op0 = SET_DEST (x);
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
op0 = SUBREG_REG (op0);
if (REG_P (op0))
{
@@ -2204,7 +2204,7 @@ operands_match_p (rtx x, rtx y)
if (x == y)
return 1;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG
+ && (REG_P (y) || (SUBREG_P (y)
&& REG_P (SUBREG_REG (y)))))
{
int j;
@@ -2222,7 +2222,7 @@ operands_match_p (rtx x, rtx y)
else
i = REGNO (x);
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
{
j = REGNO (SUBREG_REG (y));
if (j >= FIRST_PSEUDO_REGISTER)
@@ -2836,7 +2836,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* If we now have a simple operand where we used to have a
PLUS or MULT, re-recognize and try again. */
if ((OBJECT_P (*recog_data.operand_loc[i])
- || GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
+ || SUBREG_P (*recog_data.operand_loc[i]))
&& (GET_CODE (recog_data.operand[i]) == MULT
|| GET_CODE (recog_data.operand[i]) == PLUS))
{
@@ -3073,7 +3073,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
the REG or MEM (or maybe even a constant) within.
(Constants can occur as a result of reg_equiv_constant.) */
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
{
/* Offset only matters when operand is a REG and
it is a hard reg. This is because it is passed
@@ -3692,7 +3692,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
it's costly to reload it, so reload the input instead. */
if (small_register_class_p (this_alternative[i])
&& (REG_P (recog_data.operand[j])
- || GET_CODE (recog_data.operand[j]) == SUBREG))
+ || SUBREG_P (recog_data.operand[j])))
{
losers++;
this_alternative_win[j] = 0;
@@ -3907,7 +3907,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* Reloads of SUBREGs of CONSTANT RTXs are handled later in
push_reload so we have to let them pass here. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
subreg = op;
op = SUBREG_REG (op);
@@ -4086,7 +4086,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
rtx operand = recog_data.operand[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if ((MEM_P (operand)
|| (REG_P (operand)
@@ -4136,7 +4136,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
{
operand = *recog_data.operand_loc[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if (REG_P (operand))
{
@@ -4163,7 +4163,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
rtx operand = recog_data.operand[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if ((MEM_P (operand)
|| (REG_P (operand)
@@ -5505,7 +5505,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as,
rtx op0 = orig_op0;
rtx op1 = orig_op1;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
@@ -5518,7 +5518,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as,
GET_MODE (orig_op0))));
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
@@ -6362,7 +6362,7 @@ find_replacement (rtx *loc)
return reloadreg;
}
- else if (reloadreg && GET_CODE (*loc) == SUBREG
+ else if (reloadreg && SUBREG_P (*loc)
&& r->where == &SUBREG_REG (*loc))
{
if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode)
@@ -6455,7 +6455,7 @@ refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno,
/* Note setting a SUBREG counts as referring to the REG it is in for
a pseudo but not for hard registers since we can
treat each word individually. */
- && ((GET_CODE (SET_DEST (x)) == SUBREG
+ && ((SUBREG_P (SET_DEST (x))
&& loc != &SUBREG_REG (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
@@ -6531,9 +6531,9 @@ reg_overlap_mentioned_for_reload_p (rtx x, rtx in)
/* If either argument is a constant, then modifying X cannot affect IN. */
if (CONSTANT_P (x) || CONSTANT_P (in))
return 0;
- else if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
+ else if (SUBREG_P (x) && MEM_P (SUBREG_REG (x)))
return refers_to_mem_for_reload_p (in);
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
{
regno = REGNO (SUBREG_REG (x));
if (regno < FIRST_PSEUDO_REGISTER)
@@ -6942,7 +6942,7 @@ find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
{
rtx dest = SET_DEST (pat);
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -6981,7 +6981,7 @@ find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
{
rtx dest = SET_DEST (v1);
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 2747f0b2e53..5cc8bb5cada 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -3270,7 +3270,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
if (plus_cst_src)
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
+ if (SUBREG_P (reg) && subreg_lowpart_p (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -3282,7 +3282,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
rtx reg = XEXP (plus_cst_src, 0);
poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
@@ -3292,7 +3292,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
offset += ep->offset;
offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
- if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
+ if (SUBREG_P (XEXP (plus_cst_src, 0)))
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
to_rtx);
/* If we have a nonzero offset, and the source is already
@@ -3721,7 +3721,7 @@ mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
/* A SUBREG of a hard register here is just changing its mode. We should
not see a SUBREG of an eliminable hard register, but check just in
case. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (dest == hard_frame_pointer_rtx)
@@ -4422,7 +4422,7 @@ strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
rather than simplifying it to another hard register, then the
mode change cannot be properly represented. For example, OTHER
might be valid in its current mode, but not in the new one. */
- if (GET_CODE (tem) == SUBREG
+ if (SUBREG_P (tem)
&& REG_P (other)
&& HARD_REGISTER_P (other))
return false;
@@ -4829,7 +4829,7 @@ forget_old_reloads_1 (rtx x, const_rtx setter,
/* note_stores does give us subregs of hard regs,
subreg_regno_offset requires a hard reg. */
- while (GET_CODE (x) == SUBREG)
+ while (SUBREG_P (x))
{
/* We ignore the subreg offset when calculating the regno,
because we are using the entire underlying hard register
@@ -5589,10 +5589,10 @@ gen_reload_chain_without_interm_reg_p (int r1, int r2)
if (GET_CODE (in) == PLUS
&& (REG_P (XEXP (in, 0))
- || GET_CODE (XEXP (in, 0)) == SUBREG
+ || SUBREG_P (XEXP (in, 0))
|| MEM_P (XEXP (in, 0)))
&& (REG_P (XEXP (in, 1))
- || GET_CODE (XEXP (in, 1)) == SUBREG
+ || SUBREG_P (XEXP (in, 1))
|| CONSTANT_P (XEXP (in, 1))
|| MEM_P (XEXP (in, 1))))
{
@@ -6281,7 +6281,7 @@ choose_reload_regs_init (class insn_chain *chain, rtx *save_reload_reg_rtx)
static rtx
replaced_subreg (rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
return find_replacement (&SUBREG_REG (x));
return x;
}
@@ -6467,7 +6467,7 @@ choose_reload_regs (class insn_chain *chain)
regno = REGNO (rld[r].in_reg);
mode = GET_MODE (rld[r].in_reg);
}
- else if (GET_CODE (rld[r].in_reg) == SUBREG
+ else if (SUBREG_P (rld[r].in_reg)
&& REG_P (SUBREG_REG (rld[r].in_reg)))
{
regno = REGNO (SUBREG_REG (rld[r].in_reg));
@@ -6493,7 +6493,7 @@ choose_reload_regs (class insn_chain *chain)
/* This won't work, since REGNO can be a pseudo reg number.
Also, it takes much more hair to keep track of all the things
that can invalidate an inherited reload of part of a pseudoreg. */
- else if (GET_CODE (rld[r].in) == SUBREG
+ else if (SUBREG_P (rld[r].in)
&& REG_P (SUBREG_REG (rld[r].in)))
regno = subreg_regno (rld[r].in);
#endif
@@ -6663,7 +6663,7 @@ choose_reload_regs (class insn_chain *chain)
Make a new REG since this might be used in an
address and not all machines support SUBREGs
there. */
- gcc_assert (GET_CODE (equiv) == SUBREG);
+ gcc_assert (SUBREG_P (equiv));
regno = subreg_regno (equiv);
equiv = gen_rtx_REG (rld[r].mode, regno);
/* If we choose EQUIV as the reload register, but the
@@ -6914,7 +6914,7 @@ choose_reload_regs (class insn_chain *chain)
check_reg = rld[r].reg_rtx;
else if (reload_override_in[r]
&& (REG_P (reload_override_in[r])
- || GET_CODE (reload_override_in[r]) == SUBREG))
+ || SUBREG_P (reload_override_in[r])))
check_reg = reload_override_in[r];
else
continue;
@@ -7131,7 +7131,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
determine whether a secondary reload is needed. */
if (reload_override_in[j]
&& (REG_P (rl->in_reg)
- || (GET_CODE (rl->in_reg) == SUBREG
+ || (SUBREG_P (rl->in_reg)
&& REG_P (SUBREG_REG (rl->in_reg)))))
{
oldequiv = old;
@@ -7141,7 +7141,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
oldequiv = old;
else if (REG_P (oldequiv))
oldequiv_reg = oldequiv;
- else if (GET_CODE (oldequiv) == SUBREG)
+ else if (SUBREG_P (oldequiv))
oldequiv_reg = SUBREG_REG (oldequiv);
reloadreg = reload_reg_rtx_for_input[j];
@@ -7163,7 +7163,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
/* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
OLDEQUIV. */
- while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
+ while (SUBREG_P (oldequiv) && GET_MODE (oldequiv) != mode)
oldequiv = SUBREG_REG (oldequiv);
if (GET_MODE (oldequiv) != VOIDmode
&& mode != GET_MODE (oldequiv))
@@ -7342,7 +7342,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
not in the right mode. */
tmp = oldequiv;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER
@@ -7351,14 +7351,14 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
{
if (! reg_equiv_mem (REGNO (tmp))
|| num_not_at_initial_offset
- || GET_CODE (oldequiv) == SUBREG)
+ || SUBREG_P (oldequiv))
real_oldequiv = rl->in;
else
real_oldequiv = reg_equiv_mem (REGNO (tmp));
}
tmp = old;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER
@@ -7367,7 +7367,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
{
if (! reg_equiv_mem (REGNO (tmp))
|| num_not_at_initial_offset
- || GET_CODE (old) == SUBREG)
+ || SUBREG_P (old))
real_old = rl->in;
else
real_old = reg_equiv_mem (REGNO (tmp));
@@ -7542,7 +7542,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
&& REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
&& (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
|| reg_equiv_constant (REGNO (oldequiv)) != 0))
- || (GET_CODE (oldequiv) == SUBREG
+ || (SUBREG_P (oldequiv)
&& REG_P (SUBREG_REG (oldequiv))
&& (REGNO (SUBREG_REG (oldequiv))
>= FIRST_PSEUDO_REGISTER)
@@ -7949,7 +7949,7 @@ do_output_reload (class insn_chain *chain, struct reload *rl, int j)
return;
}
/* Likewise for a SUBREG of an operand that dies. */
- else if (GET_CODE (old) == SUBREG
+ else if (SUBREG_P (old)
&& REG_P (SUBREG_REG (old))
&& (note = find_reg_note (insn, REG_UNUSED,
SUBREG_REG (old))) != 0)
@@ -8098,7 +8098,7 @@ emit_reload_insns (class insn_chain *chain)
{
rtx reg = rld[r].in_reg;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg)
@@ -8507,10 +8507,10 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
if (GET_CODE (in) == PLUS
&& (REG_P (XEXP (in, 0))
- || GET_CODE (XEXP (in, 0)) == SUBREG
+ || SUBREG_P (XEXP (in, 0))
|| MEM_P (XEXP (in, 0)))
&& (REG_P (XEXP (in, 1))
- || GET_CODE (XEXP (in, 1)) == SUBREG
+ || SUBREG_P (XEXP (in, 1))
|| CONSTANT_P (XEXP (in, 1))
|| MEM_P (XEXP (in, 1))))
{
@@ -8569,7 +8569,7 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
code = optab_handler (add_optab, GET_MODE (out));
- if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
+ if (CONSTANT_P (op1) || MEM_P (op1) || SUBREG_P (op1)
|| (REG_P (op1)
&& REGNO (op1) >= FIRST_PSEUDO_REGISTER)
|| (code != CODE_FOR_nothing
@@ -8661,7 +8661,7 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
fatal_insn ("failure trying to reload:", set);
}
/* If IN is a simple operand, use gen_move_insn. */
- else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
+ else if (OBJECT_P (in) || SUBREG_P (in))
{
tem = emit_insn (gen_move_insn (out, in));
/* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
@@ -8714,7 +8714,7 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
/* Get the raw pseudo-register referred to. */
- while (GET_CODE (reg) == SUBREG)
+ while (SUBREG_P (reg))
reg = SUBREG_REG (reg);
substed = reg_equiv_memory_loc (REGNO (reg));
@@ -8731,7 +8731,7 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
reg2 = XEXP (rld[k].in_reg, 0);
- while (GET_CODE (reg2) == SUBREG)
+ while (SUBREG_P (reg2))
reg2 = SUBREG_REG (reg2);
if (rtx_equal_p (reg2, reg))
{
diff --git a/gcc/resource.c b/gcc/resource.c
index c4bcfd7dc71..3c3d6a1c6e4 100644
--- a/gcc/resource.c
+++ b/gcc/resource.c
@@ -90,10 +90,10 @@ update_live_status (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
int i;
if (!REG_P (dest)
- && (GET_CODE (dest) != SUBREG || !REG_P (SUBREG_REG (dest))))
+ && (!SUBREG_P (dest) || !REG_P (SUBREG_REG (dest))))
return;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
{
first_regno = subreg_regno (dest);
last_regno = first_regno + subreg_nregs (dest);
@@ -291,7 +291,7 @@ mark_referenced_resources (rtx x, struct resources *res,
if (GET_CODE (x) == ZERO_EXTRACT
|| GET_CODE (x) == STRICT_LOW_PART)
mark_referenced_resources (x, res, false);
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
x = SUBREG_REG (x);
if (MEM_P (x))
mark_referenced_resources (XEXP (x, 0), res, false);
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index c33d6cbc967..69095f8e38a 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -1027,7 +1027,7 @@ unsigned_reg_p (rtx op)
&& TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op))))
return true;
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_SIGN (op))
return true;
@@ -1155,7 +1155,7 @@ reg_referenced_p (const_rtx x, const_rtx body)
if (GET_CODE (SET_DEST (body)) != CC0
&& GET_CODE (SET_DEST (body)) != PC
&& !REG_P (SET_DEST (body))
- && ! (GET_CODE (SET_DEST (body)) == SUBREG
+ && ! (SUBREG_P (SET_DEST (body))
&& REG_P (SUBREG_REG (SET_DEST (body)))
&& !read_modify_subreg_p (SET_DEST (body)))
&& reg_overlap_mentioned_p (x, SET_DEST (body)))
@@ -1401,7 +1401,7 @@ modified_in_p (const_rtx x, const_rtx insn)
bool
read_modify_subreg_p (const_rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
poly_uint64 isize = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
poly_uint64 osize = GET_MODE_SIZE (GET_MODE (x));
@@ -1606,7 +1606,7 @@ set_noop_p (const_rtx set)
if (GET_CODE (dst) == STRICT_LOW_PART)
dst = XEXP (dst, 0);
- if (GET_CODE (src) == SUBREG && GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (src) && SUBREG_P (dst))
{
if (maybe_ne (SUBREG_BYTE (src), SUBREG_BYTE (dst)))
return 0;
@@ -1748,7 +1748,7 @@ refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x,
/* Note setting a SUBREG counts as referring to the REG it is in for
a pseudo but not for hard registers since we can
treat each word individually. */
- && ((GET_CODE (SET_DEST (x)) == SUBREG
+ && ((SUBREG_P (SET_DEST (x))
&& loc != &SUBREG_REG (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
@@ -1912,7 +1912,7 @@ note_stores (const_rtx x, void (*fun) (rtx, const_rtx, void *), void *data)
{
rtx dest = SET_DEST (x);
- while ((GET_CODE (dest) == SUBREG
+ while ((SUBREG_P (dest)
&& (!REG_P (SUBREG_REG (dest))
|| REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER))
|| GET_CODE (dest) == ZERO_EXTRACT
@@ -2010,7 +2010,7 @@ note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
(*fun) (&XEXP (dest, 2), data);
}
- while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART)
+ while (SUBREG_P (dest) || GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
if (MEM_P (dest))
@@ -2072,7 +2072,7 @@ covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno)
{
unsigned int regno, endregno;
- if (GET_CODE (dest) == SUBREG && !read_modify_subreg_p (dest))
+ if (SUBREG_P (dest) && !read_modify_subreg_p (dest))
dest = SUBREG_REG (dest);
if (!REG_P (dest))
@@ -3090,7 +3090,7 @@ replace_rtx (rtx x, rtx from, rtx to, bool all_regs)
gcc_assert (GET_MODE (x) == GET_MODE (from));
return to;
}
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
{
rtx new_rtx = replace_rtx (SUBREG_REG (x), from, to, all_regs);
@@ -6208,7 +6208,7 @@ get_base_term (rtx *inner)
inner = strip_address_mutations (&XEXP (*inner, 0));
if (REG_P (*inner)
|| MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
+ || SUBREG_P (*inner)
|| GET_CODE (*inner) == SCRATCH)
return inner;
return 0;
@@ -6225,7 +6225,7 @@ get_index_term (rtx *inner)
inner = strip_address_mutations (&XEXP (*inner, 0));
if (REG_P (*inner)
|| MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
+ || SUBREG_P (*inner)
|| GET_CODE (*inner) == SCRATCH)
return inner;
return 0;
diff --git a/gcc/rtlhooks.c b/gcc/rtlhooks.c
index 0ce3d1ec637..d410cd55094 100644
--- a/gcc/rtlhooks.c
+++ b/gcc/rtlhooks.c
@@ -51,7 +51,7 @@ gen_lowpart_general (machine_mode mode, rtx x)
return result;
/* Handle SUBREGs and hard REGs that were rejected by
simplify_gen_subreg. */
- else if (REG_P (x) || GET_CODE (x) == SUBREG)
+ else if (REG_P (x) || SUBREG_P (x))
{
result = gen_lowpart_common (mode, copy_to_reg (x));
gcc_assert (result != 0);
diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
index 5cb4a462ce9..247c3dbbe3f 100644
--- a/gcc/sched-deps.c
+++ b/gcc/sched-deps.c
@@ -2089,7 +2089,7 @@ mark_insn_reg_birth (rtx insn, rtx reg, bool clobber_p, bool unused_p)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
@@ -2148,7 +2148,7 @@ mark_reg_death (rtx reg)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
@@ -2423,7 +2423,7 @@ sched_analyze_1 (class deps_desc *deps, rtx x, rtx_insn *insn)
return;
}
- while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
+ while (GET_CODE (dest) == STRICT_LOW_PART || SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT)
{
if (GET_CODE (dest) == STRICT_LOW_PART
@@ -3457,7 +3457,7 @@ sched_analyze_insn (class deps_desc *deps, rtx x, rtx_insn *insn)
}
tmp = SET_DEST (set);
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp))
dest_regno = REGNO (tmp);
@@ -3465,7 +3465,7 @@ sched_analyze_insn (class deps_desc *deps, rtx x, rtx_insn *insn)
goto end_call_group;
tmp = SET_SRC (set);
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if ((GET_CODE (tmp) == PLUS
|| GET_CODE (tmp) == MINUS)
diff --git a/gcc/sched-rgn.c b/gcc/sched-rgn.c
index 59ee6a0a57c..f30b8d3f94c 100644
--- a/gcc/sched-rgn.c
+++ b/gcc/sched-rgn.c
@@ -1672,7 +1672,7 @@ check_live_1 (int src, rtx x)
if (reg == 0)
return 1;
- while (GET_CODE (reg) == SUBREG
+ while (SUBREG_P (reg)
|| GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART)
reg = XEXP (reg, 0);
@@ -1755,7 +1755,7 @@ update_live_1 (int src, rtx x)
if (reg == 0)
return;
- while (GET_CODE (reg) == SUBREG
+ while (SUBREG_P (reg)
|| GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART)
reg = XEXP (reg, 0);
diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c
index f127ff74599..e99c9002471 100644
--- a/gcc/sel-sched.c
+++ b/gcc/sel-sched.c
@@ -811,7 +811,7 @@ count_occurrences_equiv (const_rtx what, const_rtx where)
return 0;
count += 1;
}
- else if (GET_CODE (x) == SUBREG
+ else if (SUBREG_P (x)
&& (!REG_P (SUBREG_REG (x))
|| REGNO (SUBREG_REG (x)) == REGNO (what)))
/* ??? Do not support substituting regs inside subregs. In that case,
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 603bc456354..02f37535b0d 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -826,7 +826,7 @@ simplify_truncation (machine_mode mode, rtx op,
/* (truncate:A (subreg:B (truncate:C X) 0)) is
(truncate:A X). */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& SCALAR_INT_MODE_P (op_mode)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op)), &subreg_mode)
@@ -1300,7 +1300,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
is (float_truncate:SF x). */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& subreg_lowpart_p (op)
&& GET_CODE (SUBREG_REG (op)) == FLOAT_TRUNCATE)
return SUBREG_REG (op);
@@ -1474,7 +1474,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* Check for a sign extension of a subreg of a promoted
variable, where the promotion is sign-extended, and the
target mode is the same as the variable's promotion. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_SIGNED_P (op)
&& !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
@@ -1537,7 +1537,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
&& ! POINTERS_EXTEND_UNSIGNED
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& (CONSTANT_P (op)
- || (GET_CODE (op) == SUBREG
+ || (SUBREG_P (op)
&& REG_P (SUBREG_REG (op))
&& REG_POINTER (SUBREG_REG (op))
&& GET_MODE (SUBREG_REG (op)) == Pmode))
@@ -1557,7 +1557,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* Check for a zero extension of a subreg of a promoted
variable, where the promotion is zero-extended, and the
target mode is the same as the variable's promotion. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_UNSIGNED_P (op)
&& !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
@@ -1667,7 +1667,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
&& POINTERS_EXTEND_UNSIGNED > 0
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& (CONSTANT_P (op)
- || (GET_CODE (op) == SUBREG
+ || (SUBREG_P (op)
&& REG_P (SUBREG_REG (op))
&& REG_POINTER (SUBREG_REG (op))
&& GET_MODE (SUBREG_REG (op)) == Pmode))
@@ -2791,7 +2791,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
mode size to (rotate A CX). */
if (GET_CODE (op1) == ASHIFT
- || GET_CODE (op1) == SUBREG)
+ || SUBREG_P (op1))
{
opleft = op1;
opright = op0;
@@ -2813,13 +2813,13 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
/* Same, but for ashift that has been "simplified" to a wider mode
by simplify_shift_const. */
- if (GET_CODE (opleft) == SUBREG
+ if (SUBREG_P (opleft)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (opleft)),
&inner_mode)
&& GET_CODE (SUBREG_REG (opleft)) == ASHIFT
&& GET_CODE (opright) == LSHIFTRT
- && GET_CODE (XEXP (opright, 0)) == SUBREG
+ && SUBREG_P (XEXP (opright, 0))
&& known_eq (SUBREG_BYTE (opleft), SUBREG_BYTE (XEXP (opright, 0)))
&& GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (inner_mode)
&& rtx_equal_p (XEXP (SUBREG_REG (opleft), 0),
@@ -6046,7 +6046,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
Only applies for vectors of two elements. */
if (GET_CODE (op0) == VEC_DUPLICATE
- && GET_CODE (op1) == SUBREG
+ && SUBREG_P (op1)
&& GET_MODE (op1) == GET_MODE (op0)
&& GET_MODE (SUBREG_REG (op1)) == GET_MODE (XEXP (op0, 0))
&& paradoxical_subreg_p (op1)
@@ -6070,7 +6070,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
with (vec_concat:outer x:inner y:inner) if N == 1,
or (vec_concat:outer y:inner x:inner) if N == 2. */
if (GET_CODE (op1) == VEC_DUPLICATE
- && GET_CODE (op0) == SUBREG
+ && SUBREG_P (op0)
&& GET_MODE (op0) == GET_MODE (op1)
&& GET_MODE (SUBREG_REG (op0)) == GET_MODE (XEXP (op1, 0))
&& paradoxical_subreg_p (op0)
@@ -6541,7 +6541,7 @@ simplify_subreg (machine_mode outermode, rtx op,
/* Changing mode twice with SUBREG => just change it once,
or not at all if changing back op starting mode. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
@@ -6761,7 +6761,7 @@ simplify_gen_subreg (machine_mode outermode, rtx op,
if (newx)
return newx;
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
|| GET_CODE (op) == CONCAT
|| GET_MODE (op) == VOIDmode)
return NULL_RTX;
diff --git a/gcc/valtrack.c b/gcc/valtrack.c
index 87879b5f0f9..19b0b40c2b6 100644
--- a/gcc/valtrack.c
+++ b/gcc/valtrack.c
@@ -691,7 +691,7 @@ dead_debug_insert_temp (struct dead_debug_local *debug, unsigned int uregno,
cleanup_auto_inc_dec (src, VOIDmode),
GET_MODE (dest));
}
- else if (GET_CODE (dest) == SUBREG)
+ else if (SUBREG_P (dest))
{
/* We should be setting REG here. Lose. */
if (REGNO (SUBREG_REG (dest)) != REGNO (reg))
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 353df6b6618..1d425d1acd9 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -975,7 +975,7 @@ use_narrower_mode_test (rtx x, const_rtx subreg)
< GET_MODE_PRECISION (as_a <scalar_int_mode> (op1_mode)))
{
poly_uint64 byte = subreg_lowpart_offset (mode, op1_mode);
- if (GET_CODE (op1) == SUBREG || GET_CODE (op1) == CONCAT)
+ if (SUBREG_P (op1) || GET_CODE (op1) == CONCAT)
{
if (!simplify_subreg (mode, op1, op1_mode, byte))
return false;
@@ -1142,7 +1142,7 @@ adjust_mems (rtx loc, const_rtx old_rtx, void *data)
tem = gen_rtx_raw_SUBREG (GET_MODE (loc), addr, SUBREG_BYTE (loc));
finish_subreg:
if (MAY_HAVE_DEBUG_BIND_INSNS
- && GET_CODE (tem) == SUBREG
+ && SUBREG_P (tem)
&& (GET_CODE (SUBREG_REG (tem)) == PLUS
|| GET_CODE (SUBREG_REG (tem)) == MINUS
|| GET_CODE (SUBREG_REG (tem)) == MULT
@@ -6470,7 +6470,7 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
/* Try harder, when passing address of a constant
pool integer it can be easily read back. */
item = XEXP (item, 1);
- if (GET_CODE (item) == SUBREG)
+ if (SUBREG_P (item))
item = SUBREG_REG (item);
gcc_assert (GET_CODE (item) == VALUE);
val = CSELIB_VAL_PTR (item);
--
2.21.0