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Re: [AArch64][PATCH 2/2] Combine AES instructions with xor and zero operands


On Mon, Jun 18, 2018 at 04:38:44AM -0500, Andre Simoes Dias Vieira wrote:
> Hi,
> 
> This patch teaches the AArch64 backend that AES instructions with a XOR and
> zero operands can be simplified by replacing the operands of the AES with
> XOR's thus eliminating the XOR. This is OK because the AES instruction XORs
> the input operands.
> 
> This will improve code-generation when dealing with code like:
> static const uint8x16_t zero = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
> 
> uint8x16_t test0 (uint8x16_t a, uint8x16_t b)
> {
>   uint8x16_t result = vaeseq_u8 (a ^ b, zero);
>   result = vaesdq_u8 (result ^ a, zero);
>   return result;
> }
> 
> Whereas this would lead to the generation of an unnecessary 'eor' instructions:
> test0:
> 	movi	v2.4s, 0
> 	eor	v1.16b, v0.16b, v1.16b
> 	aese	v1.16b, v2.16b
> 	eor	v0.16b, v0.16b, v1.16b
> 	aesd	v0.16b, v2.16b
> 	ret
> 
> Whereas with this patch we get:
> test0:
> 	aese	v1.16b, v0.16b
> 	aesd	v0.16b, v1.16b
> 	ret
> 
> Bootstrapped and tested on aarch64-none-linux-gnu.
> 
> Is this OK for trunk?

Cute trick.

OK.

Thanks,
James

> gcc
> 2018-06-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
> 
> 
>         * config/aarch64/aarch64-simd.md (*aarch64_crypto_aes<aes_op>v16qi_xor_combine):
>         New.
> 
> gcc/testsuite
> 2018-06-18  Andre Vieira  <andre.simoesdiasvieira@arm.com>
> 
>         * gcc.target/aarch64/aes_xor_combine.c: New test.



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