This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[PATCH] MIPS: Add i6500 processor as an alias for i6400
- From: Robert Suchanek <Robert dot Suchanek at mips dot com>
- To: Matthew Fortune <Matthew dot Fortune at mips dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Fri, 1 Jun 2018 12:12:44 +0000
- Subject: [PATCH] MIPS: Add i6500 processor as an alias for i6400
Hi,
This patch adds i6500 CPU as an alias for i6400.
Regards,
Robert
gcc/ChangeLog:
2018-06-01 Matthew Fortune <matthew.fortune@mips.com>
* config/mips/mips-cpus.def: New MIPS_CPU for i6500.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Mark i6500 as
mips64r6.
* doc/invoke.texi: Document -march=i6500.
---
gcc/config/mips/mips-cpus.def | 1 +
gcc/config/mips/mips-tables.opt | 3 +++
gcc/config/mips/mips.h | 2 +-
gcc/doc/invoke.texi | 2 +-
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
index d0640e5..7314335 100644
--- a/gcc/config/mips/mips-cpus.def
+++ b/gcc/config/mips/mips-cpus.def
@@ -171,3 +171,4 @@ MIPS_CPU ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY_SPEED)
/* MIPS64 Release 6 processors. */
MIPS_CPU ("i6400", PROCESSOR_I6400, 69, 0)
+MIPS_CPU ("i6500", PROCESSOR_I6400, 69, 0)
diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt
index daccefb..d8e50b2 100644
--- a/gcc/config/mips/mips-tables.opt
+++ b/gcc/config/mips/mips-tables.opt
@@ -696,3 +696,6 @@ Enum(mips_arch_opt_value) String(xlp) Value(101) Canonical
EnumValue
Enum(mips_arch_opt_value) String(i6400) Value(102) Canonical
+EnumValue
+Enum(mips_arch_opt_value) String(i6500) Value(103) Canonical
+
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index f290560..705434e 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -782,7 +782,7 @@ struct mips_cpu_info {
%{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
%{march=mips64r3: -mips64r3} \
%{march=mips64r5: -mips64r5} \
- %{march=mips64r6|march=i6400: -mips64r6}}"
+ %{march=mips64r6|march=i6400|march=i6500: -mips64r6}}"
/* A spec that injects the default multilib ISA if no architecture is
specified. */
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 53ef14c..0d3a912 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -20220,7 +20220,7 @@ The processor names are:
@samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1}, @samp{34kn},
@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
@samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1},
-@samp{i6400},
+@samp{i6400}, @samp{i6500},
@samp{interaptiv},
@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a},
@samp{m4k},
--
2.7.4