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Re: [PATCH][AArch64] Improve LDP/STP generation that requires a base register
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, <nd at arm dot com>
- Date: Tue, 29 May 2018 17:02:20 +0100
- Subject: Re: [PATCH][AArch64] Improve LDP/STP generation that requires a base register
- Nodisclaimer: True
- References: <5B0D719B.4070500@foss.arm.com>
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On Tue, May 29, 2018 at 10:28:27AM -0500, Kyrill Tkachov wrote:
> [sending on behalf of Jackson Woodruff]
>
> Hi all,
>
> This patch generalizes the formation of LDP/STP that require a base register.
>
> In AArch64, LDP/STP instructions have different sized immediate offsets than
> normal LDR/STR instructions. This part of the backend attempts to spot groups
> of four LDR/STR instructions that can be turned into LDP/STP instructions by
> using a base register.
>
> Previously, we would only accept address pairs that were ordered in ascending
> or descending order, and only strictly sequential loads/stores. In fact, the
> instructions that we generate from this should be able to consider any order
> of loads or stores (provided that they can be re-ordered). They should also be
> able to accept non-sequential loads and stores provided that the two pairs of
> addresses are amenable to pairing. The current code is also overly restrictive
> on the range of addresses that are accepted, as LDP/STP instructions may take
> negative offsets as well as positive ones.
>
> This patch improves that by allowing us to accept all orders of loads/stores
> that are valid, and extending the range that the LDP/STP addresses can reach.
OK.
Thanks,
James